src/mainboard/tyan/s2880/auto.c

   1 #define ASSEMBLY 1
   2
   3 #include <stdint.h>
   4 #include <device/pci_def.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <cpu/x86/lapic.h>
   9 #include <arch/cpu.h>
  10 #include "option_table.h"
  11 #include "pc80/mc146818rtc_early.c"
  12 #include "pc80/serial.c"
  13 #include "arch/i386/lib/console.c"
  14 #include "ram/ramtest.c"
  15 #include "northbridge/amd/amdk8/incoherent_ht.c"
  16 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  17 #include "northbridge/amd/amdk8/raminit.h"
  18 #include "cpu/amd/model_fxx/apic_timer.c"
  19 #include "lib/delay.c"
  20 #include "cpu/x86/lapic/boot_cpu.c"
  21 #include "northbridge/amd/amdk8/reset_test.c"
  22 #include "northbridge/amd/amdk8/debug.c"
  23 #include "northbridge/amd/amdk8/cpu_rev.c"
  24 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  25 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  26 #include "cpu/x86/bist.h"
  27
  28 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  29
  30 static void hard_reset(void)
  31 {
  32         set_bios_reset();
  33
  34         /* enable cf9 */
  35         pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
  36         /* reset */
  37         outb(0x0e, 0x0cf9);
  38 }
  39
  40 static void soft_reset(void)
  41 {
  42         set_bios_reset();
  43         pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
  44 }
  45 static void soft2_reset(void)
  46 {
  47         set_bios_reset();
  48         pci_write_config8(PCI_DEV(3, 0x04, 0), 0x47, 1);
  49 }
  50
  51 static void memreset_setup(void)
  52 {
  53    if (is_cpu_pre_c0()) {
  54         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  55    }
  56    else {
  57         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  58    }
  59         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  60 }
  61
  62 static void memreset(int controllers, const struct mem_controller *ctrl)
  63 {
  64    if (is_cpu_pre_c0()) {
  65         udelay(800);
  66         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  67         udelay(90);
  68    }
  69 }
  70
  71 static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
  72 {
  73         /* Routing Table Node i
  74          *
  75          * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
  76          *  i:    0,    1,    2,    3,    4,    5,    6,    7
  77          *
  78          * [ 0: 3] Request Route
  79          *     [0] Route to this node
  80          *     [1] Route to Link 0
  81          *     [2] Route to Link 1
  82          *     [3] Route to Link 2
  83          * [11: 8] Response Route
  84          *     [0] Route to this node
  85          *     [1] Route to Link 0
  86          *     [2] Route to Link 1
  87          *     [3] Route to Link 2
  88          * [19:16] Broadcast route
  89          *     [0] Route to this node
  90          *     [1] Route to Link 0
  91          *     [2] Route to Link 1
  92          *     [3] Route to Link 2
  93          */
  94
  95         uint32_t ret=0x00010101; /* default row entry */
  96         /* Link1 of CPU0 to Link1 of CPU1 */
  97         static const unsigned int rows_2p[2][2] = {
  98                 { 0x00050101, 0x00010404 },
  99                 { 0x00010404, 0x00050101 }
 100         };
 101
 102         if(maxnodes>2) {
 103                 print_debug("this mainboard is only designed for 2 cpus\r\n");
 104                 maxnodes=2;
 105         }
 106
 107
 108         if (!(node>=maxnodes || row>=maxnodes)) {
 109                 ret=rows_2p[node][row];
 110         }
 111
 112         return ret;
 113 }
 114
 115 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 116 {
 117         /* nothing to do */
 118 }
 119
 120 static inline int spd_read_byte(unsigned device, unsigned address)
 121 {
 122         return smbus_read_byte(device, address);
 123 }
 124
 125
 126 //#include "northbridge/amd/amdk8/setup_resource_map.c"
 127 #include "northbridge/amd/amdk8/raminit.c"
 128 #include "northbridge/amd/amdk8/coherent_ht.c"
 129 #include "sdram/generic_sdram.c"
 130
 131 #include "northbridge/amd/amdk8/resourcemap.c"
 132
 133 #define FIRST_CPU  1
 134 #define SECOND_CPU 1
 135 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
 136 static void main(unsigned long bist)
 137 {
 138         static const struct mem_controller cpu[] = {
 139 #if FIRST_CPU
 140                 {
 141                         .node_id = 0,
 142                         .f0 = PCI_DEV(0, 0x18, 0),
 143                         .f1 = PCI_DEV(0, 0x18, 1),
 144                         .f2 = PCI_DEV(0, 0x18, 2),
 145                         .f3 = PCI_DEV(0, 0x18, 3),
 146                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 147                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 148                 },
 149 #endif
 150 #if SECOND_CPU
 151                 {
 152                         .node_id = 1,
 153                         .f0 = PCI_DEV(0, 0x19, 0),
 154                         .f1 = PCI_DEV(0, 0x19, 1),
 155                         .f2 = PCI_DEV(0, 0x19, 2),
 156                         .f3 = PCI_DEV(0, 0x19, 3),
 157                         .channel0 = { (0xa<<3)|4, 0, 0, 0 },
 158                         .channel1 = { (0xa<<3)|5, 0, 0, 0 },
 159                 },
 160 #endif
 161         };
 162         int needs_reset;
 163
 164         if (bist == 0) {
 165                 /* Skip this if there was a built in self test failure */
 166                 amd_early_mtrr_init();
 167                 enable_lapic();
 168                 init_timer();
 169
 170                 if (cpu_init_detected()) {
 171 #if 1
 172                         asm volatile ("jmp __cpu_reset");
 173 #else
 174                 /* cpu reset also reset the memtroller ????
 175                         need soft_reset to reset all except keep HT link freq and width */
 176                         distinguish_cpu_resets();
 177                         soft2_reset();
 178 #endif
 179                 }
 180                 distinguish_cpu_resets();
 181                 if (!boot_cpu()) {
 182                         stop_this_cpu();
 183                 }
 184         }
 185
 186         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 187         uart_init();
 188         console_init();
 189
 190         /* Halt if there was a built in self test failure */
 191 //      report_bist_failure(bist);
 192
 193         setup_default_resource_map();
 194         needs_reset = setup_coherent_ht_domain();
 195         needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
 196         if (needs_reset) {
 197                 print_info("ht reset -\r\n");
 198                 soft_reset();
 199         }
 200
 201 #if 0
 202         print_pci_devices();
 203 #endif
 204         enable_smbus();
 205 #if 0
 206         dump_spd_registers(&cpu[0]);
 207 #endif
 208         memreset_setup();
 209         sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 210
 211 #if 0
 212         dump_pci_devices();
 213 #endif
 214 #if 0
 215         dump_pci_device(PCI_DEV(0, 0x18, 1));
 216 #endif
 217
 218         /* Check all of memory */
 219 #if 0
 220         msr_t msr;
 221         msr = rdmsr(TOP_MEM2);
 222         print_debug("TOP_MEM2: ");
 223         print_debug_hex32(msr.hi);
 224         print_debug_hex32(msr.lo);
 225         print_debug("\r\n");
 226 #endif
 227 /*
 228 #if  0
 229         ram_check(0x00000000, msr.lo+(msr.hi<<32));
 230 #else
 231 #if TOTAL_CPUS < 2
 232         // Check 16MB of memory @ 0
 233         ram_check(0x00000000, 0x01000000);
 234 #else
 235         // Check 16MB of memory @ 2GB
 236         ram_check(0x80000000, 0x81000000);
 237 #endif
 238 #endif
 239 */
 240 }