src/mainboard/tyan/s2880/auto.c

   1 #define ASSEMBLY 1
   2 #include <stdint.h>
   3 #include <device/pci_def.h>
   4 #include <cpu/p6/apic.h>
   5 #include <arch/io.h>
   6 #include <arch/romcc_io.h>
   7 #include "pc80/serial.c"
   8 #include "arch/i386/lib/console.c"
   9 #include "ram/ramtest.c"
  10 #include "northbridge/amd/amdk8/early_ht.c"
  11 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  12 #include "northbridge/amd/amdk8/raminit.h"
  13 #include "cpu/k8/apic_timer.c"
  14 #include "lib/delay.c"
  15 #include "cpu/p6/boot_cpu.c"
  16 #include "northbridge/amd/amdk8/reset_test.c"
  17 #include "debug.c"
  18
  19 static void memreset_setup(void)
  20 {
  21         /* Set the memreset low */
  22         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
  23         /* Ensure the BIOS has control of the memory lines */
  24         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
  25 }
  26
  27 static void memreset(int controllers, const struct mem_controller *ctrl)
  28 {
  29         udelay(800);
  30         /* Set memreset_high */
  31         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
  32         udelay(90);
  33 }
  34
  35 static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
  36 {
  37         /* Routing Table Node i
  38          *
  39          * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
  40          *  i:    0,    1,    2,    3,    4,    5,    6,    7
  41          *
  42          * [ 0: 3] Request Route
  43          *     [0] Route to this node
  44          *     [1] Route to Link 0
  45          *     [2] Route to Link 1
  46          *     [3] Route to Link 2
  47          * [11: 8] Response Route
  48          *     [0] Route to this node
  49          *     [1] Route to Link 0
  50          *     [2] Route to Link 1
  51          *     [3] Route to Link 2
  52          * [19:16] Broadcast route
  53          *     [0] Route to this node
  54          *     [1] Route to Link 0
  55          *     [2] Route to Link 1
  56          *     [3] Route to Link 2
  57          */
  58
  59         uint32_t ret=0x00010101; /* default row entry */
  60
  61         static const unsigned int rows_2p[2][2] = {
  62                 { 0x00050101, 0x00010404 },
  63                 { 0x00010404, 0x00050101 }
  64         };
  65
  66         if(maxnodes>2) {
  67                 print_debug("this mainboard is only designed for 2 cpus\r\n");
  68                 maxnodes=2;
  69         }
  70
  71
  72         if (!(node>=maxnodes || row>=maxnodes)) {
  73                 ret=rows_2p[node][row];
  74         }
  75
  76         return ret;
  77 }
  78
  79 static inline int spd_read_byte(unsigned device, unsigned address)
  80 {
  81         return smbus_read_byte(device, address);
  82 }
  83
  84 #include "northbridge/amd/amdk8/cpu_ldtstop.c"
  85 #include "southbridge/amd/amd8111/amd8111_ldtstop.c"
  86
  87 #include "northbridge/amd/amdk8/raminit.c"
  88 #include "northbridge/amd/amdk8/coherent_ht.c"
  89 #include "sdram/generic_sdram.c"
  90
  91 static void enable_lapic(void)
  92 {
  93         msr_t msr;
  94         msr = rdmsr(0x1b);
  95         msr.hi &= 0xffffff00;
  96         msr.lo &= 0x000007ff;
  97         msr.lo |= APIC_DEFAULT_BASE | (1 << 11);
  98         wrmsr(0x1b, msr);
  99 }
 100
 101 static void stop_this_cpu(void)
 102 {
 103         unsigned apicid;
 104         apicid = apic_read(APIC_ID) >> 24;
 105
 106         /* Send an APIC INIT to myself */
 107         apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
 108         apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT);
 109         /* Wait for the ipi send to finish */
 110         apic_wait_icr_idle();
 111
 112         /* Deassert the APIC INIT */
 113         apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
 114         apic_write(APIC_ICR,  APIC_INT_LEVELTRIG | APIC_DM_INIT);
 115         /* Wait for the ipi send to finish */
 116         apic_wait_icr_idle();
 117
 118         /* If I haven't halted spin forever */
 119         for(;;) {
 120                 hlt();
 121         }
 122 }
 123 #define FIRST_CPU  1
 124 #define SECOND_CPU 1
 125 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
 126 static void main(void)
 127 {
 128         /*
 129          * GPIO28 of 8111 will control H0_MEMRESET_L
 130          * GPIO29 of 8111 will control H1_MEMRESET_L
 131          */
 132         static const struct mem_controller cpu[] = {
 133 #if FIRST_CPU
 134                 {
 135                         .node_id = 0,
 136                         .f0 = PCI_DEV(0, 0x18, 0),
 137                         .f1 = PCI_DEV(0, 0x18, 1),
 138                         .f2 = PCI_DEV(0, 0x18, 2),
 139                         .f3 = PCI_DEV(0, 0x18, 3),
 140                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 141                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 142                 },
 143 #endif
 144 #if SECOND_CPU
 145                 {
 146                         .node_id = 1,
 147                         .f0 = PCI_DEV(0, 0x19, 0),
 148                         .f1 = PCI_DEV(0, 0x19, 1),
 149                         .f2 = PCI_DEV(0, 0x19, 2),
 150                         .f3 = PCI_DEV(0, 0x19, 3),
 151                         .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 152                         .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 153                 },
 154 #endif
 155         };
 156         if (cpu_init_detected()) {
 157                 asm("jmp __cpu_reset");
 158         }
 159         enable_lapic();
 160         init_timer();
 161         if (!boot_cpu() ) {
 162                 notify_bsp_ap_is_stopped();
 163                 stop_this_cpu();
 164         }
 165         uart_init();
 166         console_init();
 167         setup_default_resource_map();
 168         setup_coherent_ht_domain();
 169         enumerate_ht_chain(0);
 170         distinguish_cpu_resets(0);
 171
 172 #if 0
 173         print_pci_devices();
 174 #endif
 175         enable_smbus();
 176 #if 0
 177         dump_spd_registers(&cpu[0]);
 178 #endif
 179         memreset_setup();
 180         sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 181
 182 #if 0
 183         dump_pci_devices();
 184 #endif
 185 #if 0
 186         dump_pci_device(PCI_DEV(0, 0x18, 2));
 187 #endif
 188
 189         /* Check all of memory */
 190 #if 0
 191         msr_t msr;
 192         msr = rdmsr(TOP_MEM);
 193         print_debug("TOP_MEM: ");
 194         print_debug_hex32(msr.hi);
 195         print_debug_hex32(msr.lo);
 196         print_debug("\r\n");
 197 #endif
 198 /*
 199 #if 1
 200         ram_check(0x00000000, msr.lo);
 201 #else
 202 #if TOTAL_CPUS < 2
 203         // Check 16MB of memory @ 0
 204         ram_check(0x00000000, 0x01000000);
 205 #else
 206         // Check 16MB of memory @ 2GB
 207         ram_check(0x80000000, 0x81000000);
 208 #endif
 209 #endif
 210 */
 211 }