src/mainboard/tyan/s2880/auto.c

   1 #define ASSEMBLY 1
   2 #include <stdint.h>
   3 #include <device/pci_def.h>
   4 #include <cpu/p6/apic.h>
   5 #include <arch/io.h>
   6 #include <arch/romcc_io.h>
   7 #include "pc80/serial.c"
   8 #include "arch/i386/lib/console.c"
   9 #include "ram/ramtest.c"
  10 #include "northbridge/amd/amdk8/early_ht.c"
  11 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  12 #include "northbridge/amd/amdk8/raminit.h"
  13 #include "cpu/k8/apic_timer.c"
  14 #include "lib/delay.c"
  15 #include "cpu/p6/boot_cpu.c"
  16 #include "northbridge/amd/amdk8/reset_test.c"
  17 #include "debug.c"
  18 #include "northbridge/amd/amdk8/cpu_rev.c"
  19
  20
  21 #define REV_B_RESET 0
  22 static void memreset_setup(void)
  23 {
  24 #if REV_B_RESET==1
  25         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  26 #else
  27         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  28 #endif
  29         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  30 }
  31
  32 static void memreset(int controllers, const struct mem_controller *ctrl)
  33 {
  34         udelay(800);
  35 #if REV_B_RESET==1
  36         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  37 #endif
  38         udelay(90);
  39 }
  40
  41 static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
  42 {
  43         /* Routing Table Node i
  44          *
  45          * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
  46          *  i:    0,    1,    2,    3,    4,    5,    6,    7
  47          *
  48          * [ 0: 3] Request Route
  49          *     [0] Route to this node
  50          *     [1] Route to Link 0
  51          *     [2] Route to Link 1
  52          *     [3] Route to Link 2
  53          * [11: 8] Response Route
  54          *     [0] Route to this node
  55          *     [1] Route to Link 0
  56          *     [2] Route to Link 1
  57          *     [3] Route to Link 2
  58          * [19:16] Broadcast route
  59          *     [0] Route to this node
  60          *     [1] Route to Link 0
  61          *     [2] Route to Link 1
  62          *     [3] Route to Link 2
  63          */
  64
  65         uint32_t ret=0x00010101; /* default row entry */
  66
  67         static const unsigned int rows_2p[2][2] = {
  68                 { 0x00050101, 0x00010404 },
  69                 { 0x00010404, 0x00050101 }
  70         };
  71
  72         if(maxnodes>2) {
  73                 print_debug("this mainboard is only designed for 2 cpus\r\n");
  74                 maxnodes=2;
  75         }
  76
  77
  78         if (!(node>=maxnodes || row>=maxnodes)) {
  79                 ret=rows_2p[node][row];
  80         }
  81
  82         return ret;
  83 }
  84
  85 static inline int spd_read_byte(unsigned device, unsigned address)
  86 {
  87         return smbus_read_byte(device, address);
  88 }
  89
  90 /* include mainboard specific ht code */
  91 #include "hypertransport.c"
  92
  93 //#include "northbridge/amd/amdk8/cpu_ldtstop.c"
  94 //#include "southbridge/amd/amd8111/amd8111_ldtstop.c"
  95
  96 #include "northbridge/amd/amdk8/raminit.c"
  97 #include "northbridge/amd/amdk8/coherent_ht.c"
  98 #include "sdram/generic_sdram.c"
  99
 100 static void enable_lapic(void)
 101 {
 102         msr_t msr;
 103         msr = rdmsr(0x1b);
 104         msr.hi &= 0xffffff00;
 105         msr.lo &= 0x000007ff;
 106         msr.lo |= APIC_DEFAULT_BASE | (1 << 11);
 107         wrmsr(0x1b, msr);
 108 }
 109
 110 static void stop_this_cpu(void)
 111 {
 112         unsigned apicid;
 113         apicid = apic_read(APIC_ID) >> 24;
 114
 115         /* Send an APIC INIT to myself */
 116         apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
 117         apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT);
 118         /* Wait for the ipi send to finish */
 119         apic_wait_icr_idle();
 120
 121         /* Deassert the APIC INIT */
 122         apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
 123         apic_write(APIC_ICR,  APIC_INT_LEVELTRIG | APIC_DM_INIT);
 124         /* Wait for the ipi send to finish */
 125         apic_wait_icr_idle();
 126
 127         /* If I haven't halted spin forever */
 128         for(;;) {
 129                 hlt();
 130         }
 131 }
 132 #define FIRST_CPU  1
 133 #define SECOND_CPU 1
 134 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
 135 static void main(void)
 136 {
 137         static const struct mem_controller cpu[] = {
 138 #if FIRST_CPU
 139                 {
 140                         .node_id = 0,
 141                         .f0 = PCI_DEV(0, 0x18, 0),
 142                         .f1 = PCI_DEV(0, 0x18, 1),
 143                         .f2 = PCI_DEV(0, 0x18, 2),
 144                         .f3 = PCI_DEV(0, 0x18, 3),
 145                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 146                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 147                 },
 148 #endif
 149 #if SECOND_CPU
 150                 {
 151                         .node_id = 1,
 152                         .f0 = PCI_DEV(0, 0x19, 0),
 153                         .f1 = PCI_DEV(0, 0x19, 1),
 154                         .f2 = PCI_DEV(0, 0x19, 2),
 155                         .f3 = PCI_DEV(0, 0x19, 3),
 156                         .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 157                         .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 158                 },
 159 #endif
 160         };
 161         if (cpu_init_detected()) {
 162                 asm("jmp __cpu_reset");
 163         }
 164         enable_lapic();
 165         init_timer();
 166         if (!boot_cpu() ) {
 167 //              notify_bsp_ap_is_stopped();
 168                 stop_this_cpu();
 169         }
 170         uart_init();
 171         console_init();
 172         setup_default_resource_map();
 173         setup_coherent_ht_domain();
 174         enumerate_ht_chain(0);
 175         distinguish_cpu_resets(0);
 176
 177 #if 0
 178         print_pci_devices();
 179 #endif
 180         enable_smbus();
 181 #if 0
 182         dump_spd_registers(&cpu[0]);
 183 #endif
 184         memreset_setup();
 185         sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 186
 187 #if 0
 188         dump_pci_devices();
 189 #endif
 190 #if 0
 191         dump_pci_device(PCI_DEV(0, 0x18, 1));
 192 #endif
 193
 194         /* Check all of memory */
 195 #if 0
 196         msr_t msr;
 197         msr = rdmsr(TOP_MEM2);
 198         print_debug("TOP_MEM2: ");
 199         print_debug_hex32(msr.hi);
 200         print_debug_hex32(msr.lo);
 201         print_debug("\r\n");
 202 #endif
 203 /*
 204 #if  0
 205         ram_check(0x00000000, msr.lo+(msr.hi<<32));
 206 #else
 207 #if TOTAL_CPUS < 2
 208         // Check 16MB of memory @ 0
 209         ram_check(0x00000000, 0x01000000);
 210 #else
 211         // Check 16MB of memory @ 2GB
 212         ram_check(0x80000000, 0x81000000);
 213 #endif
 214 #endif
 215 */
 216 }