src/mainboard/tyan/s2880/auto.c

   1 #define ASSEMBLY 1
   2
   3 #include <stdint.h>
   4 #include <device/pci_def.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <arch/smp/lapic.h>
   9 #include "option_table.h"
  10 #include "pc80/mc146818rtc_early.c"
  11 #include "pc80/serial.c"
  12 #include "arch/i386/lib/console.c"
  13 #include "ram/ramtest.c"
  14 #include "northbridge/amd/amdk8/incoherent_ht.c"
  15 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  16 #include "northbridge/amd/amdk8/raminit.h"
  17 #include "cpu/k8/apic_timer.c"
  18 #include "lib/delay.c"
  19 #include "cpu/p6/boot_cpu.c"
  20 #include "northbridge/amd/amdk8/reset_test.c"
  21 #include "northbridge/amd/amdk8/debug.c"
  22 #include "northbridge/amd/amdk8/cpu_rev.c"
  23 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  24
  25 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  26
  27 static void hard_reset(void)
  28 {
  29         set_bios_reset();
  30
  31         /* enable cf9 */
  32         pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
  33         /* reset */
  34         outb(0x0e, 0x0cf9);
  35 }
  36
  37 static void soft_reset(void)
  38 {
  39         set_bios_reset();
  40         pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
  41 }
  42 static void memreset_setup(void)
  43 {
  44    if (is_cpu_pre_c0()) {
  45         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  46    }
  47    else {
  48         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  49    }
  50         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  51 }
  52
  53 static void memreset(int controllers, const struct mem_controller *ctrl)
  54 {
  55    if (is_cpu_pre_c0()) {
  56         udelay(800);
  57         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  58         udelay(90);
  59    }
  60 }
  61
  62 static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
  63 {
  64         /* Routing Table Node i
  65          *
  66          * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
  67          *  i:    0,    1,    2,    3,    4,    5,    6,    7
  68          *
  69          * [ 0: 3] Request Route
  70          *     [0] Route to this node
  71          *     [1] Route to Link 0
  72          *     [2] Route to Link 1
  73          *     [3] Route to Link 2
  74          * [11: 8] Response Route
  75          *     [0] Route to this node
  76          *     [1] Route to Link 0
  77          *     [2] Route to Link 1
  78          *     [3] Route to Link 2
  79          * [19:16] Broadcast route
  80          *     [0] Route to this node
  81          *     [1] Route to Link 0
  82          *     [2] Route to Link 1
  83          *     [3] Route to Link 2
  84          */
  85
  86         uint32_t ret=0x00010101; /* default row entry */
  87
  88         static const unsigned int rows_2p[2][2] = {
  89                 { 0x00050101, 0x00010404 },
  90                 { 0x00010404, 0x00050101 }
  91         };
  92
  93         if(maxnodes>2) {
  94                 print_debug("this mainboard is only designed for 2 cpus\r\n");
  95                 maxnodes=2;
  96         }
  97
  98
  99         if (!(node>=maxnodes || row>=maxnodes)) {
 100                 ret=rows_2p[node][row];
 101         }
 102
 103         return ret;
 104 }
 105
 106 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 107 {
 108         /* nothing to do */
 109 }
 110
 111 static inline int spd_read_byte(unsigned device, unsigned address)
 112 {
 113         return smbus_read_byte(device, address);
 114 }
 115
 116 /* include mainboard specific ht code */
 117 //#include "hypertransport.c"
 118
 119 #include "northbridge/amd/amdk8/raminit.c"
 120 #include "northbridge/amd/amdk8/coherent_ht.c"
 121 #include "sdram/generic_sdram.c"
 122
 123 #define FIRST_CPU  1
 124 #define SECOND_CPU 1
 125 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
 126 static void main(void)
 127 {
 128         static const struct mem_controller cpu[] = {
 129 #if FIRST_CPU
 130                 {
 131                         .node_id = 0,
 132                         .f0 = PCI_DEV(0, 0x18, 0),
 133                         .f1 = PCI_DEV(0, 0x18, 1),
 134                         .f2 = PCI_DEV(0, 0x18, 2),
 135                         .f3 = PCI_DEV(0, 0x18, 3),
 136                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 137                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 138                 },
 139 #endif
 140 #if SECOND_CPU
 141                 {
 142                         .node_id = 1,
 143                         .f0 = PCI_DEV(0, 0x19, 0),
 144                         .f1 = PCI_DEV(0, 0x19, 1),
 145                         .f2 = PCI_DEV(0, 0x19, 2),
 146                         .f3 = PCI_DEV(0, 0x19, 3),
 147                         .channel0 = { (0xa<<3)|4, 0, 0, 0 },
 148                         .channel1 = { (0xa<<3)|5, 0, 0, 0 },
 149                 },
 150 #endif
 151         };
 152         int needs_reset;
 153         enable_lapic();
 154         init_timer();
 155         if (cpu_init_detected()) {
 156                 asm("jmp __cpu_reset");
 157         }
 158         distinguish_cpu_resets();
 159         if (!boot_cpu()) {
 160                 stop_this_cpu();
 161         }
 162         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 163         uart_init();
 164         console_init();
 165         setup_default_resource_map();
 166         needs_reset = setup_coherent_ht_domain();
 167         needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
 168         if (needs_reset) {
 169                 print_info("ht reset -\r\n");
 170                 soft_reset();
 171         }
 172
 173 #if 0
 174         print_pci_devices();
 175 #endif
 176         enable_smbus();
 177 #if 0
 178         dump_spd_registers(&cpu[0]);
 179 #endif
 180         memreset_setup();
 181         sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 182
 183 #if 0
 184         dump_pci_devices();
 185 #endif
 186 #if 0
 187         dump_pci_device(PCI_DEV(0, 0x18, 1));
 188 #endif
 189
 190         /* Check all of memory */
 191 #if 0
 192         msr_t msr;
 193         msr = rdmsr(TOP_MEM2);
 194         print_debug("TOP_MEM2: ");
 195         print_debug_hex32(msr.hi);
 196         print_debug_hex32(msr.lo);
 197         print_debug("\r\n");
 198 #endif
 199 /*
 200 #if  0
 201         ram_check(0x00000000, msr.lo+(msr.hi<<32));
 202 #else
 203 #if TOTAL_CPUS < 2
 204         // Check 16MB of memory @ 0
 205         ram_check(0x00000000, 0x01000000);
 206 #else
 207         // Check 16MB of memory @ 2GB
 208         ram_check(0x80000000, 0x81000000);
 209 #endif
 210 #endif
 211 */
 212 }