4 #include <device/pci_def.h>
6 #include <device/pnp_def.h>
7 #include <arch/romcc_io.h>
8 #include <cpu/x86/lapic.h>
10 #include "option_table.h"
11 #include "pc80/mc146818rtc_early.c"
12 #include "pc80/serial.c"
13 #include "arch/i386/lib/console.c"
14 #include "ram/ramtest.c"
15 #include "northbridge/amd/amdk8/incoherent_ht.c"
16 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
17 #include "northbridge/amd/amdk8/raminit.h"
18 #include "cpu/amd/model_fxx/apic_timer.c"
19 #include "lib/delay.c"
20 #include "cpu/x86/lapic/boot_cpu.c"
21 #include "northbridge/amd/amdk8/reset_test.c"
22 #include "northbridge/amd/amdk8/debug.c"
23 #include "northbridge/amd/amdk8/cpu_rev.c"
24 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
25 #include "cpu/amd/mtrr/amd_earlymtrr.c"
26 #include "cpu/x86/bist.h"
28 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
30 static void hard_reset(void)
35 pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
40 static void soft_reset(void)
43 pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
46 static void memreset_setup(void)
48 if (is_cpu_pre_c0()) {
49 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
52 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
54 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
57 static void memreset(int controllers, const struct mem_controller *ctrl)
59 if (is_cpu_pre_c0()) {
61 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
66 static inline void activate_spd_rom(const struct mem_controller *ctrl)
71 static inline int spd_read_byte(unsigned device, unsigned address)
73 return smbus_read_byte(device, address);
77 #include "northbridge/amd/amdk8/setup_resource_map.c"
78 #include "northbridge/amd/amdk8/raminit.c"
79 #include "northbridge/amd/amdk8/coherent_ht.c"
80 #include "sdram/generic_sdram.c"
82 #include "northbridge/amd/amdk8/resourcemap.c"
84 #if CONFIG_LOGICAL_CPUS==1
85 #define SET_NB_CFG_54 1
86 #include "cpu/amd/dualcore/dualcore.c"
91 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
92 static void main(unsigned long bist)
94 static const struct mem_controller cpu[] = {
98 .f0 = PCI_DEV(0, 0x18, 0),
99 .f1 = PCI_DEV(0, 0x18, 1),
100 .f2 = PCI_DEV(0, 0x18, 2),
101 .f3 = PCI_DEV(0, 0x18, 3),
102 .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
103 .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
109 .f0 = PCI_DEV(0, 0x19, 0),
110 .f1 = PCI_DEV(0, 0x19, 1),
111 .f2 = PCI_DEV(0, 0x19, 2),
112 .f3 = PCI_DEV(0, 0x19, 3),
113 .channel0 = { (0xa<<3)|4, 0, 0, 0 },
114 .channel1 = { (0xa<<3)|5, 0, 0, 0 },
120 #if CONFIG_LOGICAL_CPUS==1
121 struct node_core_id id;
127 /* Skip this if there was a built in self test failure */
128 amd_early_mtrr_init();
130 #if CONFIG_LOGICAL_CPUS==1
131 set_apicid_cpuid_lo();
137 #if CONFIG_LOGICAL_CPUS==1
138 id = get_node_core_id_x();
140 if (cpu_init_detected(id.nodeid)) {
141 asm volatile ("jmp __cpu_reset");
143 distinguish_cpu_resets(id.nodeid);
147 if (cpu_init_detected(nodeid)) {
148 asm volatile ("jmp __cpu_reset");
150 distinguish_cpu_resets(nodeid);
154 #if CONFIG_LOGICAL_CPUS==1
162 w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
166 /* Halt if there was a built in self test failure */
167 report_bist_failure(bist);
169 setup_default_resource_map();
170 needs_reset = setup_coherent_ht_domain();
172 #if CONFIG_LOGICAL_CPUS==1
176 needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
178 print_info("ht reset -\r\n");
184 sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);