src/mainboard/tyan/s2880/Config.lb

   1 uses HAVE_MP_TABLE
   2 uses HAVE_PIRQ_TABLE
   3 uses USE_FALLBACK_IMAGE
   4 uses LB_CKS_RANGE_START
   5 uses LB_CKS_RANGE_END
   6 uses LB_CKS_LOC
   7 uses MAINBOARD
   8 uses ARCH
   9 uses HARD_RESET_BUS
  10 uses HARD_RESET_DEVICE
  11 uses HARD_RESET_FUNCTION
  12 #
  13 #
  14 ###
  15 ### Set all of the defaults for an x86 architecture
  16 ###
  17 #
  18 #
  19 ###
  20 ### Build the objects we have code for in this directory.
  21 ###
  22 config chip.h
  23 register "fixup_scsi" = "1"
  24 register "fixup_vga" = "1"
  25
  26 ##
  27 ## Move the default LinuxBIOS cmos range off of AMD RTC registers
  28 ##
  29 default LB_CKS_RANGE_START=49
  30 default LB_CKS_RANGE_END=122
  31 default LB_CKS_LOC=123
  32
  33
  34 driver mainboard.o
  35 #dir /drivers/lsi/53c1030
  36 #dir /drivers/adaptec/7902
  37 #dir /drivers/si/3114
  38 #dir /drivers/intel/82551
  39 dir /drivers/ati/ragexl
  40 #object reset.o
  41 if HAVE_MP_TABLE object mptable.o end
  42 if HAVE_PIRQ_TABLE object irq_tables.o end
  43 #
  44 default HARD_RESET_BUS=1
  45 default HARD_RESET_DEVICE=4
  46 default HARD_RESET_FUNCTION=0
  47 #
  48 arch i386 end
  49 #
  50 ###
  51 ### Build our 16 bit and 32 bit linuxBIOS entry code
  52 ###
  53 mainboardinit cpu/i386/entry16.inc
  54 mainboardinit cpu/i386/entry32.inc
  55 mainboardinit cpu/i386/bist32.inc
  56 ldscript /cpu/i386/entry16.lds
  57 ldscript /cpu/i386/entry32.lds
  58 #
  59 ###
  60 ### Build our reset vector (This is where linuxBIOS is entered)
  61 ###
  62 if USE_FALLBACK_IMAGE
  63         mainboardinit cpu/i386/reset16.inc
  64         ldscript /cpu/i386/reset16.lds
  65 else
  66         mainboardinit cpu/i386/reset32.inc
  67         ldscript /cpu/i386/reset32.lds
  68 end
  69 #
  70 #### Should this be in the northbridge code?
  71 mainboardinit arch/i386/lib/cpu_reset.inc
  72 #
  73 ###
  74 ### Include an id string (For safe flashing)
  75 ###
  76 mainboardinit arch/i386/lib/id.inc
  77 ldscript /arch/i386/lib/id.lds
  78 #
  79 ####
  80 #### This is the early phase of linuxBIOS startup
  81 #### Things are delicate and we test to see if we should
  82 #### failover to another image.
  83 ####
  84 #option MAX_REBOOT_CNT=2
  85 if USE_FALLBACK_IMAGE
  86   ldscript /arch/i386/lib/failover.lds
  87 end
  88 #
  89 ###
  90 ### Setup our mtrrs
  91 ###
  92 mainboardinit cpu/k8/earlymtrr.inc
  93 ###
  94 ### Only the bootstrap cpu makes it here.
  95 ### Failover if we need to
  96 ###
  97 #
  98 if USE_FALLBACK_IMAGE
  99   mainboardinit ./failover.inc
 100 end
 101
 102 #
 103 #
 104 ###
 105 ### Setup the serial port
 106 ###
 107 mainboardinit pc80/serial.inc
 108 mainboardinit arch/i386/lib/console.inc
 109 mainboardinit cpu/i386/bist32_fail.inc
 110 #
 111 ###
 112 ### Romcc output
 113 ###
 114
 115 makerule ./failover.E
 116         depends "$(MAINBOARD)/failover.c"
 117         action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
 118 end
 119
 120 makerule ./failover.inc
 121         depends "./romcc ./failover.E"
 122         action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"end
 123
 124 makerule ./auto.E
 125         depends "$(MAINBOARD)/auto.c option_table.h"
 126         action  "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
 127 end
 128 makerule ./auto.inc
 129         depends "./romcc ./auto.E"
 130         action "./romcc -O2 -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E"
 131 end
 132 mainboardinit cpu/k8/enable_mmx_sse.inc
 133 mainboardinit ./auto.inc
 134 mainboardinit cpu/k8/disable_mmx_sse.inc
 135 #
 136 ###
 137 ### Include the secondary Configuration files
 138 ###
 139 northbridge amd/amdk8 "mc0"
 140         pci 0:18.0
 141         pci 0:18.0
 142         pci 0:18.0
 143         pci 0:18.1
 144         pci 0:18.2
 145         pci 0:18.3
 146         southbridge amd/amd8131 "amd8131" link 0
 147                 pci 0:0.0
 148                 pci 0:0.1
 149                 pci 0:1.0
 150                 pci 0:1.1
 151         end
 152         southbridge amd/amd8111 "amd8111" link 0
 153                 pci 0:0.0
 154                 pci 0:1.0 on
 155                 pci 0:1.1 on
 156                 pci 0:1.2 on
 157                 pci 0:1.3 on
 158                 pci 0:1.5 off
 159                 pci 0:1.6 off
 160                 pci 1:0.0 on
 161                 pci 1:0.1 on
 162                 pci 1:0.2 off
 163                 pci 1:1.0 off
 164                 superio winbond/w83627hf link 1
 165                         pnp 2e.0 off #  Floppy
 166                                  io 0x60 = 0x3f0
 167                                 irq 0x70 = 6
 168                                 drq 0x74 = 2
 169                         pnp 2e.1 off #  Parallel Port
 170                                  io 0x60 = 0x378
 171                                 irq 0x70 = 7
 172                         pnp 2e.2 on #  Com1
 173                                  io 0x60 = 0x3f8
 174                                 irq 0x70 = 4
 175                         pnp 2e.3 off #  Com2
 176                                  io 0x60 = 0x2f8
 177                                 irq 0x70 = 3
 178                         pnp 2e.5 on #  Keyboard
 179                                  io 0x60 = 0x60
 180                                  io 0x62 = 0x64
 181                                 irq 0x70 = 1
 182                                 irq 0x72 = 12
 183                         pnp 2e.6 off #  CIR
 184                         pnp 2e.7 off #  GAME_MIDI_GIPO1
 185                         pnp 2e.8 off #  GPIO2
 186                         pnp 2e.9 off #  GPIO3
 187                         pnp 2e.a off #  ACPI
 188                         pnp 2e.b on  #  HW Monitor
 189                                  io 0x60 = 0x290
 190                 end
 191         end
 192 end
 193
 194 northbridge amd/amdk8 "mc1"
 195         pci 0:19.0
 196         pci 0:19.0
 197         pci 0:19.0
 198         pci 0:19.1
 199         pci 0:19.2
 200         pci 0:19.3
 201 end
 202
 203
 204 dir /pc80
 205 #dir /bioscall
 206 cpu k8 "cpu0"
 207   register "ldt0" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}"
 208 end
 209
 210 cpu k8 "cpu1"
 211 end