src/mainboard/tyan/s2880/Config.lb

   1 ##
   2 ## Compute the location and size of where this firmware image
   3 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
   4 ##
   5 if USE_FALLBACK_IMAGE
   6         default ROM_SECTION_SIZE   = FALLBACK_SIZE
   7         default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
   8 else
   9         default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
  10         default ROM_SECTION_OFFSET = 0
  11 end
  12
  13 ##
  14 ## Compute the start location and size size of
  15 ## The linuxBIOS bootloader.
  16 ##
  17 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
  18 default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
  19
  20 ##
  21 ## Compute where this copy of linuxBIOS will start in the boot rom
  22 ##
  23 default _ROMBASE      = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
  24
  25 ##
  26 ## Compute a range of ROM that can cached to speed up linuxBIOS,
  27 ## execution speed.
  28 ##
  29 ## XIP_ROM_SIZE must be a power of 2.
  30 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
  31 ##
  32 default XIP_ROM_SIZE=65536
  33 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
  34
  35 arch i386 end
  36
  37 ##
  38 ## Build the objects we have code for in this directory.
  39 ##
  40
  41 driver mainboard.o
  42 if HAVE_MP_TABLE object mptable.o end
  43 if HAVE_PIRQ_TABLE object irq_tables.o end
  44 #object reset.o
  45
  46
  47 ##
  48 ## Romcc output
  49 ##
  50 makerule ./failover.E
  51         depends "$(MAINBOARD)/failover.c ./romcc"
  52         action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
  53 end
  54
  55 makerule ./failover.inc
  56         depends "$(MAINBOARD)/failover.c ./romcc"
  57         action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
  58 end
  59
  60 makerule ./auto.E
  61         depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
  62         action  "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
  63 end
  64 makerule ./auto.inc
  65         depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
  66         action  "./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
  67 end
  68
  69 ##
  70 ## Build our 16 bit and 32 bit linuxBIOS entry code
  71 ##
  72 mainboardinit cpu/x86/16bit/entry16.inc
  73 mainboardinit cpu/x86/32bit/entry32.inc
  74 ldscript /cpu/x86/16bit/entry16.lds
  75 ldscript /cpu/x86/32bit/entry32.lds
  76
  77 ##
  78 ## Build our reset vector (This is where linuxBIOS is entered)
  79 ##
  80 if USE_FALLBACK_IMAGE
  81         mainboardinit cpu/x86/16bit/reset16.inc
  82         ldscript /cpu/x86/16bit/reset16.lds
  83 else
  84         mainboardinit cpu/x86/32bit/reset32.inc
  85         ldscript /cpu/x86/32bit/reset32.lds
  86 end
  87
  88 ### Should this be in the northbridge code?
  89 mainboardinit arch/i386/lib/cpu_reset.inc
  90
  91 ##
  92 ## Include an id string (For safe flashing)
  93 ##
  94 mainboardinit arch/i386/lib/id.inc
  95 ldscript /arch/i386/lib/id.lds
  96
  97 ###
  98 ### This is the early phase of linuxBIOS startup
  99 ### Things are delicate and we test to see if we should
 100 ### failover to another image.
 101 ###
 102 if USE_FALLBACK_IMAGE
 103         ldscript /arch/i386/lib/failover.lds
 104         mainboardinit ./failover.inc
 105 end
 106
 107 ###
 108 ### O.k. We aren't just an intermediary anymore!
 109 ###
 110
 111 ##
 112 ## Setup RAM
 113 ##
 114 mainboardinit cpu/x86/fpu/enable_fpu.inc
 115 mainboardinit cpu/x86/mmx/enable_mmx.inc
 116 mainboardinit cpu/x86/sse/enable_sse.inc
 117 mainboardinit ./auto.inc
 118 mainboardinit cpu/x86/sse/disable_sse.inc
 119 mainboardinit cpu/x86/mmx/disable_mmx.inc
 120
 121 ##
 122 ## Include the secondary Configuration files
 123 ##
 124 dir /pc80
 125 config chip.h
 126
 127 # sample config for tyan/s2880
 128 chip northbridge/amd/amdk8
 129         device pci_domain 0 on
 130                 device pci 18.0 on #  northbridge
 131                         #  devices on link 0, link 0 == LDT 0
 132                         chip southbridge/amd/amd8131
 133                                 # the on/off keyword is mandatory
 134                                 device pci 0.0 on end
 135                                 device pci 0.1 on end
 136                                 device pci 1.0 on end
 137                                 device pci 1.1 on end
 138                         end
 139                         chip southbridge/amd/amd8111
 140                                 # this "device pci 0.0" is the parent the next one
 141                                 # PCI bridge
 142                                 device pci 0.0 on
 143                                         device pci 0.0 on end
 144                                         device pci 0.1 on end
 145                                         device pci 0.2 off end
 146                                         device pci 1.0 off end
 147                                 end
 148                                 device pci 1.0 on
 149                                         chip superio/winbond/w83627hf
 150                                                 device pnp 2e.0 on #  Floppy
 151                                                         io 0x60 = 0x3f0
 152                                                         irq 0x70 = 6
 153                                                         drq 0x74 = 2
 154                                                 end
 155                                                 device pnp 2e.1 off #  Parallel Port
 156                                                         io 0x60 = 0x378
 157                                                         irq 0x70 = 7
 158                                                 end
 159                                                 device pnp 2e.2 on #  Com1
 160                                                         io 0x60 = 0x3f8
 161                                                         irq 0x70 = 4
 162                                                 end
 163                                                 device pnp 2e.3 off #  Com2
 164                                                         io 0x60 = 0x2f8
 165                                                         irq 0x70 = 3
 166                                                 end
 167                                                 device pnp 2e.5 on #  Keyboard
 168                                                         io 0x60 = 0x60
 169                                                         io 0x62 = 0x64
 170                                                         irq 0x70 = 1
 171                                                         irq 0x72 = 12
 172                                                 end
 173                                                 device pnp 2e.6 off #  CIR
 174                                                         io 0x60 = 0x100
 175                                                 end
 176                                                 device pnp 2e.7 off #  GAME_MIDI_GIPO1
 177                                                         io 0x60 = 0x201
 178                                                         io 0x62 = 0x330
 179                                                         irq 0x70 = 9
 180                                                 end
 181                                                 device pnp 2e.8 off end #  GPIO2
 182                                                 device pnp 2e.9 off end #  GPIO3
 183                                                 device pnp 2e.a off end #  ACPI
 184                                                 device pnp 2e.b on #  HW Monitor
 185                                                         io 0x60 = 0x290
 186                                                         irq 0x70 = 5
 187                                                 end
 188                                         end
 189                                 end
 190                                 device pci 1.1 on end
 191                                 device pci 1.2 on end
 192                                 device pci 1.3 on end
 193                                 device pci 1.5 off end
 194                                 device pci 1.6 off end
 195                         end
 196                 end #  device pci 18.0
 197
 198                 device pci 18.0 on end
 199                 device pci 18.0 on end
 200
 201                 device pci 18.1 on end
 202                 device pci 18.2 on end
 203                 device pci 18.3 on end
 204
 205                 chip northbridge/amd/amdk8
 206                         device pci 19.0 on end
 207                         device pci 19.0 on end
 208                         device pci 19.0 on end
 209                         device pci 19.1 on end
 210                         device pci 19.2 on end
 211                         device pci 19.3 on end
 212                 end
 213         end
 214         device apic_cluster 0 on
 215                 chip cpu/amd/socket_940
 216                         device apic 0 on end
 217                 end
 218                 chip cpu/amd/socket_940
 219                         device apic 1 on end
 220                 end
 221         end
 222 end
 223