2 ## Compute the location and size of where this firmware image
3 ## (coreboot plus bootloader) will live in the boot rom chip.
6 default ROM_SECTION_SIZE = FALLBACK_SIZE
7 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
9 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
10 default ROM_SECTION_OFFSET = 0
14 ## Compute the start location and size size of
15 ## The coreboot bootloader.
17 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
18 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
21 ## Compute where this copy of coreboot will start in the boot rom
23 default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
26 ## Compute a range of ROM that can cached to speed up coreboot,
29 ## XIP_ROM_SIZE must be a power of 2.
30 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
32 default XIP_ROM_SIZE=65536
33 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
38 ## Build the objects we have code for in this directory.
45 if HAVE_MP_TABLE object mptable.o end
46 if HAVE_PIRQ_TABLE object irq_tables.o end
51 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
52 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
58 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
59 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
60 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
61 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
66 ## Build our 16 bit and 32 bit coreboot entry code
69 mainboardinit cpu/x86/16bit/entry16.inc
70 ldscript /cpu/x86/16bit/entry16.lds
73 mainboardinit cpu/x86/32bit/entry32.inc
76 ldscript /cpu/x86/32bit/entry32.lds
80 ldscript /cpu/amd/car/cache_as_ram.lds
84 ## Build our reset vector (This is where coreboot is entered)
87 mainboardinit cpu/x86/16bit/reset16.inc
88 ldscript /cpu/x86/16bit/reset16.lds
90 mainboardinit cpu/x86/32bit/reset32.inc
91 ldscript /cpu/x86/32bit/reset32.lds
95 ## Include an id string (For safe flashing)
97 mainboardinit arch/i386/lib/id.inc
98 ldscript /arch/i386/lib/id.lds
101 ## Setup Cache-As-Ram
103 mainboardinit cpu/amd/car/cache_as_ram.inc
106 ### This is the early phase of coreboot startup
107 ### Things are delicate and we test to see if we should
108 ### failover to another image.
110 if USE_FALLBACK_IMAGE
111 ldscript /arch/i386/lib/failover.lds
115 ### O.k. We aren't just an intermediary anymore!
124 mainboardinit ./auto.inc
128 ## Include the secondary Configuration files
132 # sample config for tyan/s2880
133 chip northbridge/amd/amdk8/root_complex
134 device apic_cluster 0 on
135 chip cpu/amd/socket_940
139 device pci_domain 0 on
140 chip northbridge/amd/amdk8
141 device pci 18.0 on # northbridge
142 # devices on link 0, link 0 == LDT 0
143 chip southbridge/amd/amd8131
144 # the on/off keyword is mandatory
146 chip drivers/pci/onboard
147 device pci 9.0 on end #broadcom
148 device pci 9.1 on end
150 # chip drivers/lsi/53c1030
151 # device pci a.0 on end
152 # device pci a.1 on end
153 # register "fw_address" = "0xfff8c000"
156 device pci 0.1 on end
157 device pci 1.0 on end
158 device pci 1.1 on end
160 chip southbridge/amd/amd8111
161 # this "device pci 0.0" is the parent the next one
164 device pci 0.0 on end
165 device pci 0.1 on end
166 device pci 0.2 off end
167 device pci 1.0 off end
168 chip drivers/pci/onboard
169 device pci 5.0 on end #some sata
171 chip drivers/pci/onboard
172 device pci 6.0 on end #adti
173 register "rom_address" = "0xfff80000"
177 chip superio/winbond/w83627hf
178 device pnp 2e.0 on # Floppy
183 device pnp 2e.1 off # Parallel Port
187 device pnp 2e.2 on # Com1
191 device pnp 2e.3 off # Com2
195 device pnp 2e.5 on # Keyboard
201 device pnp 2e.6 off # CIR
204 device pnp 2e.7 off # GAME_MIDI_GIPO1
209 device pnp 2e.8 off end # GPIO2
210 device pnp 2e.9 off end # GPIO3
211 device pnp 2e.a off end # ACPI
212 device pnp 2e.b on # HW Monitor
218 device pci 1.1 on end
219 device pci 1.2 on end
220 device pci 1.3 on end
221 device pci 1.5 off end
222 device pci 1.6 off end
223 register "ide0_enable" = "1"
224 register "ide1_enable" = "1"
226 end # device pci 18.0
228 device pci 18.0 on end
229 device pci 18.0 on end
231 device pci 18.1 on end
232 device pci 18.2 on end
233 device pci 18.3 on end