src/mainboard/tyan/s2880/Config.lb

   1 ##
   2 ## Compute the location and size of where this firmware image
   3 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
   4 ##
   5 if USE_FALLBACK_IMAGE
   6         default ROM_SECTION_SIZE   = FALLBACK_SIZE
   7         default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
   8 else
   9         default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
  10         default ROM_SECTION_OFFSET = 0
  11 end
  12
  13 ##
  14 ## Compute the start location and size size of
  15 ## The linuxBIOS bootloader.
  16 ##
  17 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
  18 default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
  19
  20 ##
  21 ## Compute where this copy of linuxBIOS will start in the boot rom
  22 ##
  23 default _ROMBASE      = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
  24
  25 ##
  26 ## Compute a range of ROM that can cached to speed up linuxBIOS,
  27 ## execution speed.
  28 ##
  29 ## XIP_ROM_SIZE must be a power of 2.
  30 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
  31 ##
  32 default XIP_ROM_SIZE=65536
  33 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
  34
  35 arch i386 end
  36
  37 ##
  38 ## Build the objects we have code for in this directory.
  39 ##
  40
  41 driver mainboard.o
  42
  43 #dir /drivers/si/3114
  44
  45 if HAVE_MP_TABLE object mptable.o end
  46 if HAVE_PIRQ_TABLE object irq_tables.o end
  47 object reset.o
  48
  49 if USE_DCACHE_RAM
  50
  51 if CONFIG_USE_INIT
  52
  53 makerule ./auto.o
  54         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  55         action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
  56 end
  57
  58 else
  59
  60 makerule ./auto.inc
  61         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  62         action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
  63         action "perl -e 's/.rodata/.rom.data/g' -pi $@"
  64         action "perl -e 's/.text/.section .rom.text/g' -pi $@"
  65 end
  66
  67 end
  68 else
  69
  70 ##
  71 ## Romcc output
  72 ##
  73 makerule ./failover.E
  74         depends "$(MAINBOARD)/failover.c ./romcc"
  75         action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
  76 end
  77
  78 makerule ./failover.inc
  79         depends "$(MAINBOARD)/failover.c ./romcc"
  80         action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
  81 end
  82
  83 makerule ./auto.E
  84         depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
  85         action  "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
  86 end
  87 makerule ./auto.inc
  88         depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
  89         action  "./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
  90 end
  91
  92 end
  93 ##
  94 ## Build our 16 bit and 32 bit linuxBIOS entry code
  95 ##
  96 if USE_FALLBACK_IMAGE
  97         mainboardinit cpu/x86/16bit/entry16.inc
  98         ldscript /cpu/x86/16bit/entry16.lds
  99 end
 100
 101 mainboardinit cpu/x86/32bit/entry32.inc
 102
 103 if USE_DCACHE_RAM
 104         if CONFIG_USE_INIT
 105                 ldscript /cpu/x86/32bit/entry32.lds
 106         end
 107
 108         if CONFIG_USE_INIT
 109                 ldscript      /cpu/amd/car/cache_as_ram.lds
 110         end
 111 end
 112
 113 ##
 114 ## Build our reset vector (This is where linuxBIOS is entered)
 115 ##
 116 if USE_FALLBACK_IMAGE
 117         mainboardinit cpu/x86/16bit/reset16.inc
 118         ldscript /cpu/x86/16bit/reset16.lds
 119 else
 120         mainboardinit cpu/x86/32bit/reset32.inc
 121         ldscript /cpu/x86/32bit/reset32.lds
 122 end
 123
 124 if USE_DCACHE_RAM
 125 else
 126 ### Should this be in the northbridge code?
 127 mainboardinit arch/i386/lib/cpu_reset.inc
 128 end
 129
 130 ##
 131 ## Include an id string (For safe flashing)
 132 ##
 133 mainboardinit arch/i386/lib/id.inc
 134 ldscript /arch/i386/lib/id.lds
 135
 136 if USE_DCACHE_RAM
 137 ##
 138 ## Setup Cache-As-Ram
 139 ##
 140 mainboardinit cpu/amd/car/cache_as_ram.inc
 141 end
 142
 143 ###
 144 ### This is the early phase of linuxBIOS startup
 145 ### Things are delicate and we test to see if we should
 146 ### failover to another image.
 147 ###
 148 if USE_FALLBACK_IMAGE
 149 if USE_DCACHE_RAM
 150        ldscript /arch/i386/lib/failover.lds
 151 else
 152        ldscript /arch/i386/lib/failover.lds
 153         mainboardinit ./failover.inc
 154 end
 155 end
 156
 157 ###
 158 ### O.k. We aren't just an intermediary anymore!
 159 ###
 160
 161 ##
 162 ## Setup RAM
 163 ##
 164 if USE_DCACHE_RAM
 165
 166 if CONFIG_USE_INIT
 167 initobject auto.o
 168 else
 169 mainboardinit ./auto.inc
 170 end
 171
 172 else
 173
 174 ##
 175 ## Setup RAM
 176 ##
 177 mainboardinit cpu/x86/fpu/enable_fpu.inc
 178 mainboardinit cpu/x86/mmx/enable_mmx.inc
 179 mainboardinit cpu/x86/sse/enable_sse.inc
 180 mainboardinit ./auto.inc
 181 mainboardinit cpu/x86/sse/disable_sse.inc
 182 mainboardinit cpu/x86/mmx/disable_mmx.inc
 183
 184 end
 185
 186 ##
 187 ## Include the secondary Configuration files
 188 ##
 189 if CONFIG_CHIP_NAME
 190         config chip.h
 191 end
 192
 193 # sample config for tyan/s2880
 194 chip northbridge/amd/amdk8/root_complex
 195         device apic_cluster 0 on
 196                 chip cpu/amd/socket_940
 197                         device apic 0 on end
 198                 end
 199         end
 200         device pci_domain 0 on
 201                 chip northbridge/amd/amdk8
 202                         device pci 18.0 on #  northbridge
 203                                 #  devices on link 0, link 0 == LDT 0
 204                                 chip southbridge/amd/amd8131
 205                                         # the on/off keyword is mandatory
 206                                         device pci 0.0 on
 207                                                 chip drivers/pci/onboard
 208                                                         device pci 9.0 on end #broadcom
 209                                                         device pci 9.1 on end
 210                                                 end
 211 #                                                chip drivers/lsi/53c1030
 212 #                                                        device pci a.0 on end
 213 #                                                        device pci a.1 on end
 214 #                                                        register "fw_address" = "0xfff8c000"
 215 #                                                end
 216                                         end
 217                                         device pci 0.1 on end
 218                                         device pci 1.0 on end
 219                                         device pci 1.1 on end
 220                                 end
 221                                 chip southbridge/amd/amd8111
 222                                         # this "device pci 0.0" is the parent the next one
 223                                         # PCI bridge
 224                                         device pci 0.0 on
 225                                                 device pci 0.0 on end
 226                                                 device pci 0.1 on end
 227                                                 device pci 0.2 off end
 228                                                 device pci 1.0 off end
 229                                                 chip drivers/pci/onboard
 230                                                         device pci 5.0 on end #some sata
 231                                                 end
 232                                                 chip drivers/pci/onboard
 233                                                         device pci 6.0 on end #adti
 234                                                         register "rom_address" = "0xfff80000"
 235                                                 end
 236                                         end
 237                                         device pci 1.0 on
 238                                                 chip superio/winbond/w83627hf
 239                                                         device pnp 2e.0 on #  Floppy
 240                                                                 io 0x60 = 0x3f0
 241                                                                 irq 0x70 = 6
 242                                                                 drq 0x74 = 2
 243                                                         end
 244                                                         device pnp 2e.1 off #  Parallel Port
 245                                                                 io 0x60 = 0x378
 246                                                                 irq 0x70 = 7
 247                                                         end
 248                                                         device pnp 2e.2 on #  Com1
 249                                                                 io 0x60 = 0x3f8
 250                                                                 irq 0x70 = 4
 251                                                         end
 252                                                         device pnp 2e.3 off #  Com2
 253                                                                 io 0x60 = 0x2f8
 254                                                                 irq 0x70 = 3
 255                                                         end
 256                                                         device pnp 2e.5 on #  Keyboard
 257                                                                 io 0x60 = 0x60
 258                                                                 io 0x62 = 0x64
 259                                                                 irq 0x70 = 1
 260                                                                 irq 0x72 = 12
 261                                                         end
 262                                                         device pnp 2e.6 off #  CIR
 263                                                                 io 0x60 = 0x100
 264                                                         end
 265                                                         device pnp 2e.7 off #  GAME_MIDI_GIPO1
 266                                                                 io 0x60 = 0x220
 267                                                                 io 0x62 = 0x300
 268                                                                 irq 0x70 = 9
 269                                                         end
 270                                                         device pnp 2e.8 off end #  GPIO2
 271                                                         device pnp 2e.9 off end #  GPIO3
 272                                                         device pnp 2e.a off end #  ACPI
 273                                                         device pnp 2e.b on #  HW Monitor
 274                                                                 io 0x60 = 0x290
 275                                                                 irq 0x70 = 5
 276                                                         end
 277                                                 end
 278                                         end
 279                                         device pci 1.1 on end
 280                                         device pci 1.2 on end
 281                                         device pci 1.3 on end
 282                                         device pci 1.5 off end
 283                                         device pci 1.6 off end
 284                                         register "ide0_enable" = "1"
 285                                         register "ide1_enable" = "1"
 286                                 end
 287                         end #  device pci 18.0
 288
 289                         device pci 18.0 on end
 290                         device pci 18.0 on end
 291
 292                         device pci 18.1 on end
 293                         device pci 18.2 on end
 294                         device pci 18.3 on end
 295                 end
 296         end
 297 end
 298