4 #include <device/pci_def.h>
6 #include <device/pnp_def.h>
7 #include <arch/romcc_io.h>
8 #include <cpu/x86/lapic.h>
10 #include "option_table.h"
11 #include "pc80/mc146818rtc_early.c"
12 #include "pc80/serial.c"
13 #include "arch/i386/lib/console.c"
14 #include "ram/ramtest.c"
15 #include "northbridge/amd/amdk8/incoherent_ht.c"
16 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
17 #include "northbridge/amd/amdk8/raminit.h"
18 #include "cpu/amd/model_fxx/apic_timer.c"
19 #include "lib/delay.c"
20 #include "cpu/x86/lapic/boot_cpu.c"
21 #include "northbridge/amd/amdk8/reset_test.c"
22 #include "northbridge/amd/amdk8/debug.c"
23 #include <cpu/amd/model_fxx_rev.h>
24 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
25 #include "cpu/amd/mtrr/amd_earlymtrr.c"
26 #include "cpu/x86/bist.h"
27 #include "cpu/amd/dualcore/dualcore.c"
29 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
31 /* Look up a which bus a given node/link combination is on.
32 * return 0 when we can't find the answer.
34 static unsigned node_link_to_bus(unsigned node, unsigned link)
38 for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
40 config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
41 if ((config_map & 3) != 3) {
44 if ((((config_map >> 4) & 7) == node) &&
45 (((config_map >> 8) & 3) == link))
47 return (config_map >> 16) & 0xff;
53 static void hard_reset(void)
58 dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3);
63 pci_write_config8(dev, 0x41, 0xf1);
68 static void soft_reset(void)
73 dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0);
76 pci_write_config8(dev, 0x47, 1);
79 static void memreset_setup(void)
81 if (is_cpu_pre_c0()) {
82 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
85 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
87 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
90 static void memreset(int controllers, const struct mem_controller *ctrl)
92 if (is_cpu_pre_c0()) {
94 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
99 static inline void activate_spd_rom(const struct mem_controller *ctrl)
104 static inline int spd_read_byte(unsigned device, unsigned address)
106 return smbus_read_byte(device, address);
110 #include "northbridge/amd/amdk8/setup_resource_map.c"
111 #include "northbridge/amd/amdk8/raminit.c"
112 #include "northbridge/amd/amdk8/coherent_ht.c"
113 #include "sdram/generic_sdram.c"
114 #include "northbridge/amd/amdk8/resourcemap.c"
118 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
119 static void main(unsigned long bist)
121 static const struct mem_controller cpu[] = {
125 .f0 = PCI_DEV(0, 0x18, 0),
126 .f1 = PCI_DEV(0, 0x18, 1),
127 .f2 = PCI_DEV(0, 0x18, 2),
128 .f3 = PCI_DEV(0, 0x18, 3),
129 .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
130 .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
136 .f0 = PCI_DEV(0, 0x19, 0),
137 .f1 = PCI_DEV(0, 0x19, 1),
138 .f2 = PCI_DEV(0, 0x19, 2),
139 .f3 = PCI_DEV(0, 0x19, 3),
140 .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
141 .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
149 k8_init_and_stop_secondaries();
152 w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
156 /* Halt if there was a built in self test failure */
157 report_bist_failure(bist);
159 setup_default_resource_map();
160 needs_reset = setup_coherent_ht_domain();
162 needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
164 print_info("ht reset -\r\n");
170 sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);