3 uses USE_FALLBACK_IMAGE
4 uses HAVE_FALLBACK_BOOT
9 uses CONFIG_MAX_PHYSICAL_CPUS
10 uses CONFIG_LOGICAL_CPUS
18 uses ROM_SECTION_OFFSET
19 uses CONFIG_ROM_PAYLOAD
20 uses CONFIG_ROM_PAYLOAD_START
21 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
22 uses CONFIG_PRECOMPRESSED_PAYLOAD
30 uses LB_CKS_RANGE_START
33 uses MAINBOARD_PART_NUMBER
36 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
37 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
38 uses COREBOOT_EXTRA_VERSION
43 uses DEFAULT_CONSOLE_LOGLEVEL
44 uses MAXIMUM_CONSOLE_LOGLEVEL
45 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
46 uses CONFIG_CONSOLE_SERIAL8250
55 uses CONFIG_CONSOLE_VGA
56 uses CONFIG_PCI_ROM_RUN
57 uses HW_MEM_HOLE_SIZEK
63 uses CONFIG_USE_PRINTK_IN_CAR
70 ## ROM_SIZE is the size of boot ROM that this board will use.
72 default ROM_SIZE=524288
75 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
77 #default FALLBACK_SIZE=131072
79 default FALLBACK_SIZE=0x40000
83 ## Build code for the fallback boot
85 default HAVE_FALLBACK_BOOT=1
88 ## Build code to reset the motherboard from coreboot
90 default HAVE_HARD_RESET=1
93 ## Build code to export a programmable irq routing table
95 default HAVE_PIRQ_TABLE=1
96 default IRQ_SLOT_COUNT=13
99 ## Build code to export an x86 MP table
100 ## Useful for specifying IRQ routing values
102 default HAVE_MP_TABLE=1
105 ## Build code to export a CMOS option table
107 default HAVE_OPTION_TABLE=1
110 ## Move the default coreboot cmos range off of AMD RTC registers
112 default LB_CKS_RANGE_START=49
113 default LB_CKS_RANGE_END=122
114 default LB_CKS_LOC=123
117 ## Build code for SMP support
118 ## Only worry about 2 micro processors
121 default CONFIG_MAX_CPUS=4
122 default CONFIG_MAX_PHYSICAL_CPUS=2
123 default CONFIG_LOGICAL_CPUS=1
126 default CONFIG_CHIP_NAME=1
129 default HW_MEM_HOLE_SIZEK=0x100000
132 default CONFIG_CONSOLE_VGA=1
133 default CONFIG_PCI_ROM_RUN=1
137 ## enable CACHE_AS_RAM specifics
139 default USE_DCACHE_RAM=1
140 default DCACHE_RAM_BASE=0xcf000
141 default DCACHE_RAM_SIZE=0x1000
142 default CONFIG_USE_INIT=0
145 ## Build code to setup a generic IOAPIC
147 default CONFIG_IOAPIC=1
150 ## Clean up the motherboard id strings
152 default MAINBOARD_PART_NUMBER="s2875"
153 default MAINBOARD_VENDOR="Tyan"
154 default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
155 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2875
158 ### coreboot layout values
161 ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
162 default ROM_IMAGE_SIZE = 65536
165 ## Use a small 8K stack
167 default STACK_SIZE=0x2000
170 ## Use a small 16K heap
172 default HEAP_SIZE=0x4000
175 ## Only use the option table in a normal image
177 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
180 ## Coreboot C code runs at this location in RAM
182 default _RAMBASE=0x00004000
185 ## Load the payload from the ROM
187 default CONFIG_ROM_PAYLOAD = 1
190 ### Defaults of options that you may want to override in the target config file
194 ## The default compiler
196 default CC="$(CROSS_COMPILE)gcc -m32"
200 ## Disable the gdb stub by default
202 default CONFIG_GDB_STUB=0
204 default CONFIG_USE_PRINTK_IN_CAR=1
207 ## The Serial Console
210 # To Enable the Serial Console
211 default CONFIG_CONSOLE_SERIAL8250=1
213 ## Select the serial console baud rate
214 default TTYS0_BAUD=115200
215 #default TTYS0_BAUD=57600
216 #default TTYS0_BAUD=38400
217 #default TTYS0_BAUD=19200
218 #default TTYS0_BAUD=9600
219 #default TTYS0_BAUD=4800
220 #default TTYS0_BAUD=2400
221 #default TTYS0_BAUD=1200
223 # Select the serial console base port
224 default TTYS0_BASE=0x3f8
226 # Select the serial protocol
227 # This defaults to 8 data bits, 1 stop bit, and no parity
228 default TTYS0_LCS=0x3
231 ### Select the coreboot loglevel
233 ## EMERG 1 system is unusable
234 ## ALERT 2 action must be taken immediately
235 ## CRIT 3 critical conditions
236 ## ERR 4 error conditions
237 ## WARNING 5 warning conditions
238 ## NOTICE 6 normal but significant condition
239 ## INFO 7 informational
240 ## DEBUG 8 debug-level messages
241 ## SPEW 9 Way too many details
243 ## Request this level of debugging output
244 default DEFAULT_CONSOLE_LOGLEVEL=8
245 ## At a maximum only compile in this level of debugging
246 default MAXIMUM_CONSOLE_LOGLEVEL=8
249 ## Select power on after power fail setting
250 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"