src/mainboard/tyan/s2875/Config.lb

   1 ##
   2 ## Compute the location and size of where this firmware image
   3 ## (coreboot plus bootloader) will live in the boot rom chip.
   4 ##
   5 if USE_FALLBACK_IMAGE
   6         default ROM_SECTION_SIZE   = FALLBACK_SIZE
   7         default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
   8 else
   9         default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
  10         default ROM_SECTION_OFFSET = 0
  11 end
  12
  13 ##
  14 ## Compute the start location and size size of
  15 ## The coreboot bootloader.
  16 ##
  17 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
  18 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
  19
  20 ##
  21 ## Compute where this copy of coreboot will start in the boot rom
  22 ##
  23 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
  24
  25 ##
  26 ## Compute a range of ROM that can cached to speed up coreboot,
  27 ## execution speed.
  28 ##
  29 ## XIP_ROM_SIZE must be a power of 2.
  30 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
  31 ##
  32 default XIP_ROM_SIZE=65536
  33 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
  34
  35 arch i386 end
  36
  37 ##
  38 ## Build the objects we have code for in this directory.
  39 ##
  40
  41 driver mainboard.o
  42
  43 #dir /drivers/si/3114
  44
  45 if HAVE_MP_TABLE object mptable.o end
  46 if HAVE_PIRQ_TABLE object irq_tables.o end
  47
  48 if CONFIG_USE_INIT
  49
  50 makerule ./auto.o
  51         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  52         action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
  53 end
  54
  55 else
  56
  57 makerule ./auto.inc
  58         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  59         action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall $(DEBUG_CFLAGS) -c -S -o $@"
  60         action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
  61         action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
  62 end
  63
  64 end
  65 ##
  66 ## Build our 16 bit and 32 bit coreboot entry code
  67 ##
  68 if USE_FALLBACK_IMAGE
  69         mainboardinit cpu/x86/16bit/entry16.inc
  70         ldscript /cpu/x86/16bit/entry16.lds
  71 end
  72
  73 mainboardinit cpu/x86/32bit/entry32.inc
  74
  75         if CONFIG_USE_INIT
  76                 ldscript /cpu/x86/32bit/entry32.lds
  77         end
  78
  79         if CONFIG_USE_INIT
  80                 ldscript      /cpu/amd/car/cache_as_ram.lds
  81         end
  82
  83 ##
  84 ## Build our reset vector (This is where coreboot is entered)
  85 ##
  86 if USE_FALLBACK_IMAGE
  87         mainboardinit cpu/x86/16bit/reset16.inc
  88         ldscript /cpu/x86/16bit/reset16.lds
  89 else
  90         mainboardinit cpu/x86/32bit/reset32.inc
  91         ldscript /cpu/x86/32bit/reset32.lds
  92 end
  93
  94 ##
  95 ## Include an id string (For safe flashing)
  96 ##
  97 mainboardinit arch/i386/lib/id.inc
  98 ldscript /arch/i386/lib/id.lds
  99
 100 ##
 101 ## Setup Cache-As-Ram
 102 ##
 103 mainboardinit cpu/amd/car/cache_as_ram.inc
 104
 105 ###
 106 ### This is the early phase of coreboot startup
 107 ### Things are delicate and we test to see if we should
 108 ### failover to another image.
 109 ###
 110 if USE_FALLBACK_IMAGE
 111        ldscript /arch/i386/lib/failover.lds
 112 end
 113
 114 ###
 115 ### O.k. We aren't just an intermediary anymore!
 116 ###
 117
 118 ##
 119 ## Setup RAM
 120 ##
 121 if CONFIG_USE_INIT
 122 initobject auto.o
 123 else
 124 mainboardinit ./auto.inc
 125 end
 126
 127 ##
 128 ## Include the secondary Configuration files
 129 ##
 130 config chip.h
 131
 132 # sample config for tyan/s2875
 133 chip northbridge/amd/amdk8/root_complex
 134         device apic_cluster 0 on
 135                 chip cpu/amd/socket_940
 136                         device apic 0 on end
 137                 end
 138         end
 139         device pci_domain 0 on
 140                 chip northbridge/amd/amdk8
 141                         device pci 18.0 on #  northbridge
 142                                 #  devices on link 0, link 0 == LDT 0
 143                                 chip southbridge/amd/amd8151
 144                                         # the on/off keyword is mandatory
 145                                         device pci 0.0 on end
 146                                         device pci 1.0 on end
 147                                 end
 148                                 chip southbridge/amd/amd8111
 149                                         # this "device pci 0.0" is the parent the next one
 150                                         # PCI bridge
 151                                         device pci 0.0 on
 152                                                 device pci 0.0 on end
 153                                                 device pci 0.1 on end
 154                                                 device pci 0.2 off end
 155                                                 device pci 1.0 off end
 156                                                 chip drivers/pci/onboard
 157                                                         device pci 5.0 on end
 158                                                         register "rom_address" = "0xfff80000"
 159                                                 end
 160                                         end
 161                                         device pci 1.0 on
 162                                                 chip superio/winbond/w83627hf
 163                                                         device pnp 2e.0 on #  Floppy
 164                                                                 io 0x60 = 0x3f0
 165                                                                 irq 0x70 = 6
 166                                                                 drq 0x74 = 2
 167                                                         end
 168                                                         device pnp 2e.1 off #  Parallel Port
 169                                                                 io 0x60 = 0x378
 170                                                                 irq 0x70 = 7
 171                                                         end
 172                                                         device pnp 2e.2 on #  Com1
 173                                                                 io 0x60 = 0x3f8
 174                                                                 irq 0x70 = 4
 175                                                         end
 176                                                         device pnp 2e.3 off #  Com2
 177                                                                 io 0x60 = 0x2f8
 178                                                                 irq 0x70 = 3
 179                                                         end
 180                                                         device pnp 2e.5 on #  Keyboard
 181                                                                 io 0x60 = 0x60
 182                                                                 io 0x62 = 0x64
 183                                                                 irq 0x70 = 1
 184                                                                 irq 0x72 = 12
 185                                                         end
 186                                                         device pnp 2e.6 off #  CIR
 187                                                                 io 0x60 = 0x100
 188                                                         end
 189                                                         device pnp 2e.7 off #  GAME_MIDI_GIPO1
 190                                                                 io 0x60 = 0x220
 191                                                                 io 0x62 = 0x300
 192                                                                 irq 0x70 = 9
 193                                                         end
 194                                                         device pnp 2e.8 off end #  GPIO2
 195                                                         device pnp 2e.9 off end #  GPIO3
 196                                                         device pnp 2e.a off end #  ACPI
 197                                                         device pnp 2e.b on #  HW Monitor
 198                                                                 io 0x60 = 0x290
 199                                                                 irq 0x70 = 5
 200                                                         end
 201                                                 end
 202                                         end
 203                                         device pci 1.1 on end
 204                                         device pci 1.2 on end
 205                                         device pci 1.3 on end
 206                                         device pci 1.5 on end
 207                                         device pci 1.6 off end
 208                                         register "ide0_enable" = "1"
 209                                         register "ide1_enable" = "1"
 210                                 end
 211                         end #  device pci 18.0
 212
 213                         device pci 18.0 on end
 214                         device pci 18.0 on end
 215
 216                         device pci 18.1 on end
 217                         device pci 18.2 on end
 218                         device pci 18.3 on end
 219                 end
 220         end
 221 end
 222