src/mainboard/tyan/s2875/Config.lb

   1 ##
   2 ## Compute the location and size of where this firmware image
   3 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
   4 ##
   5 if USE_FALLBACK_IMAGE
   6         default ROM_SECTION_SIZE   = FALLBACK_SIZE
   7         default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
   8 else
   9         default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
  10         default ROM_SECTION_OFFSET = 0
  11 end
  12
  13 ##
  14 ## Compute the start location and size size of
  15 ## The linuxBIOS bootloader.
  16 ##
  17 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
  18 default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
  19
  20 ##
  21 ## Compute where this copy of linuxBIOS will start in the boot rom
  22 ##
  23 default _ROMBASE      = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
  24
  25 ##
  26 ## Compute a range of ROM that can cached to speed up linuxBIOS,
  27 ## execution speed.
  28 ##
  29 ## XIP_ROM_SIZE must be a power of 2.
  30 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
  31 ##
  32 default XIP_ROM_SIZE=65536
  33 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
  34
  35 arch i386 end
  36
  37 ##
  38 ## Build the objects we have code for in this directory.
  39 ##
  40
  41 driver mainboard.o
  42 if HAVE_MP_TABLE object mptable.o end
  43 if HAVE_PIRQ_TABLE object irq_tables.o end
  44 #object reset.o
  45
  46
  47 ##
  48 ## Romcc output
  49 ##
  50 makerule ./failover.E
  51         depends "$(MAINBOARD)/failover.c ./romcc"
  52         action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
  53 end
  54
  55 makerule ./failover.inc
  56         depends "$(MAINBOARD)/failover.c ./romcc"
  57         action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
  58 end
  59
  60 makerule ./auto.E
  61         depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
  62         action  "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
  63 end
  64 makerule ./auto.inc
  65         depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
  66         action  "./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
  67 end
  68
  69 ##
  70 ## Build our 16 bit and 32 bit linuxBIOS entry code
  71 ##
  72 mainboardinit cpu/x86/16bit/entry16.inc
  73 mainboardinit cpu/x86/32bit/entry32.inc
  74 ldscript /cpu/x86/16bit/entry16.lds
  75 ldscript /cpu/x86/32bit/entry32.lds
  76
  77 ##
  78 ## Build our reset vector (This is where linuxBIOS is entered)
  79 ##
  80 if USE_FALLBACK_IMAGE
  81         mainboardinit cpu/x86/16bit/reset16.inc
  82         ldscript /cpu/x86/16bit/reset16.lds
  83 else
  84         mainboardinit cpu/x86/32bit/reset32.inc
  85         ldscript /cpu/x86/32bit/reset32.lds
  86 end
  87
  88 ### Should this be in the northbridge code?
  89 mainboardinit arch/i386/lib/cpu_reset.inc
  90
  91 ##
  92 ## Include an id string (For safe flashing)
  93 ##
  94 mainboardinit arch/i386/lib/id.inc
  95 ldscript /arch/i386/lib/id.lds
  96
  97 ###
  98 ### This is the early phase of linuxBIOS startup
  99 ### Things are delicate and we test to see if we should
 100 ### failover to another image.
 101 ###
 102 if USE_FALLBACK_IMAGE
 103         ldscript /arch/i386/lib/failover.lds
 104         mainboardinit ./failover.inc
 105 end
 106
 107 ###
 108 ### O.k. We aren't just an intermediary anymore!
 109 ###
 110
 111 ##
 112 ## Setup RAM
 113 ##
 114 mainboardinit cpu/x86/fpu/enable_fpu.inc
 115 mainboardinit cpu/x86/mmx/enable_mmx.inc
 116 mainboardinit cpu/x86/sse/enable_sse.inc
 117 mainboardinit ./auto.inc
 118 mainboardinit cpu/x86/sse/disable_sse.inc
 119 mainboardinit cpu/x86/mmx/disable_mmx.inc
 120
 121 ##
 122 ## Include the secondary Configuration files
 123 ##
 124 if CONFIG_CHIP_NAME
 125         config chip.h
 126 end
 127
 128 # sample config for tyan/s2875
 129 chip northbridge/amd/amdk8/root_complex
 130         device apic_cluster 0 on
 131                 chip cpu/amd/socket_940
 132                         device apic 0 on end
 133                 end
 134         end
 135         device pci_domain 0 on
 136                 chip northbridge/amd/amdk8
 137                         device pci 18.0 on #  northbridge
 138                                 #  devices on link 0, link 0 == LDT 0
 139                                 chip southbridge/amd/amd8151
 140                                         # the on/off keyword is mandatory
 141                                         device pci 0.0 on end
 142                                         device pci 1.0 on end
 143                                 end
 144                                 chip southbridge/amd/amd8111
 145                                         # this "device pci 0.0" is the parent the next one
 146                                         # PCI bridge
 147                                         device pci 0.0 on
 148                                                 device pci 0.0 on end
 149                                                 device pci 0.1 on end
 150                                                 device pci 0.2 off end
 151                                                 device pci 1.0 off end
 152                                                 chip drivers/pci/onboard
 153                                                         device pci 5.0 on end
 154                                                         register "rom_address" = "0xfff80000"
 155                                                 end
 156                                         end
 157                                         device pci 1.0 on
 158                                                 chip superio/winbond/w83627hf
 159                                                         device pnp 2e.0 on #  Floppy
 160                                                                 io 0x60 = 0x3f0
 161                                                                 irq 0x70 = 6
 162                                                                 drq 0x74 = 2
 163                                                         end
 164                                                         device pnp 2e.1 off #  Parallel Port
 165                                                                 io 0x60 = 0x378
 166                                                                 irq 0x70 = 7
 167                                                         end
 168                                                         device pnp 2e.2 on #  Com1
 169                                                                 io 0x60 = 0x3f8
 170                                                                 irq 0x70 = 4
 171                                                         end
 172                                                         device pnp 2e.3 off #  Com2
 173                                                                 io 0x60 = 0x2f8
 174                                                                 irq 0x70 = 3
 175                                                         end
 176                                                         device pnp 2e.5 on #  Keyboard
 177                                                                 io 0x60 = 0x60
 178                                                                 io 0x62 = 0x64
 179                                                                 irq 0x70 = 1
 180                                                                 irq 0x72 = 12
 181                                                         end
 182                                                         device pnp 2e.6 off #  CIR
 183                                                                 io 0x60 = 0x100
 184                                                         end
 185                                                         device pnp 2e.7 off #  GAME_MIDI_GIPO1
 186                                                                 io 0x60 = 0x220
 187                                                                 io 0x62 = 0x300
 188                                                                 irq 0x70 = 9
 189                                                         end
 190                                                         device pnp 2e.8 off end #  GPIO2
 191                                                         device pnp 2e.9 off end #  GPIO3
 192                                                         device pnp 2e.a off end #  ACPI
 193                                                         device pnp 2e.b on #  HW Monitor
 194                                                                 io 0x60 = 0x290
 195                                                                 irq 0x70 = 5
 196                                                         end
 197                                                 end
 198                                         end
 199                                         device pci 1.1 on end
 200                                         device pci 1.2 on end
 201                                         device pci 1.3 on end
 202                                         device pci 1.5 on end
 203                                         device pci 1.6 off end
 204                                         register "ide0_enable" = "1"
 205                                         register "ide1_enable" = "1"
 206                                 end
 207                         end #  device pci 18.0
 208
 209                         device pci 18.0 on end
 210                         device pci 18.0 on end
 211
 212                         device pci 18.1 on end
 213                         device pci 18.2 on end
 214                         device pci 18.3 on end
 215                 end
 216         end
 217 end
 218