src/mainboard/tyan/s2875/Config.lb

   1 uses HAVE_MP_TABLE
   2 uses HAVE_PIRQ_TABLE
   3 uses USE_FALLBACK_IMAGE
   4 uses LB_CKS_RANGE_START
   5 uses LB_CKS_RANGE_END
   6 uses LB_CKS_LOC
   7 uses MAINBOARD
   8 uses ARCH
   9 uses HARD_RESET_BUS
  10 uses HARD_RESET_DEVICE
  11 uses HARD_RESET_FUNCTION
  12
  13 #
  14 #
  15 ###
  16 ### Set all of the defaults for an x86 architecture
  17 ###
  18
  19 #
  20 #
  21 ###
  22 ### Build the objects we have code for in this directory.
  23 ###
  24
  25 config chip.h
  26 register "fixup_scsi" = "1"
  27 register "fixup_vga" = "1"
  28
  29
  30 ##
  31 ## Move the default LinuxBIOS cmos range off of AMD RTC registers
  32 ##
  33 default LB_CKS_RANGE_START=49
  34 default LB_CKS_RANGE_END=122
  35 default LB_CKS_LOC=123
  36
  37 driver mainboard.o
  38 #dir /drivers/adaptec/7902
  39 #dir /drivers/si/3114
  40 #dir /driver/intel/82551
  41 #object reset.o
  42 if HAVE_MP_TABLE object mptable.o end
  43 if HAVE_PIRQ_TABLE object irq_tables.o end
  44 #
  45 default HARD_RESET_BUS=1
  46 default HARD_RESET_DEVICE=5
  47 default HARD_RESET_FUNCTION=0
  48 #
  49 #
  50 arch i386 end
  51
  52 #
  53 ###
  54 ### Build our 16 bit and 32 bit linuxBIOS entry code
  55 ###
  56 mainboardinit cpu/i386/entry16.inc
  57 mainboardinit cpu/i386/entry32.inc
  58 mainboardinit cpu/i386/bist32.inc
  59 ldscript /cpu/i386/entry16.lds
  60 ldscript /cpu/i386/entry32.lds
  61
  62 #
  63 ###
  64 ### Build our reset vector (This is where linuxBIOS is entered)
  65 ###
  66 if USE_FALLBACK_IMAGE
  67         mainboardinit cpu/i386/reset16.inc
  68         ldscript /cpu/i386/reset16.lds
  69 else
  70         mainboardinit cpu/i386/reset32.inc
  71         ldscript /cpu/i386/reset32.lds
  72 end
  73 #
  74 #### Should this be in the northbridge code?
  75 mainboardinit arch/i386/lib/cpu_reset.inc
  76 #
  77 ###
  78 ### Include an id string (For safe flashing)
  79 ###
  80 mainboardinit arch/i386/lib/id.inc
  81 ldscript /arch/i386/lib/id.lds
  82 #
  83 ####
  84 #### This is the early phase of linuxBIOS startup
  85 #### Things are delicate and we test to see if we should
  86 #### failover to another image.
  87 ####
  88 #option MAX_REBOOT_CNT=2
  89 if USE_FALLBACK_IMAGE
  90   ldscript /arch/i386/lib/failover.lds
  91 end
  92 #
  93 ###
  94 ### Setup our mtrrs
  95 ###
  96 mainboardinit cpu/k8/earlymtrr.inc
  97 ###
  98 ### Only the bootstrap cpu makes it here.
  99 ### Failover if we need to
 100 ###
 101 #
 102 if USE_FALLBACK_IMAGE
 103   mainboardinit ./failover.inc
 104 end
 105
 106 #
 107 #
 108 ###
 109 ### Setup the serial port
 110 ###
 111 mainboardinit pc80/serial.inc
 112 mainboardinit arch/i386/lib/console.inc
 113 mainboardinit cpu/i386/bist32_fail.inc
 114 #
 115 ####
 116 #### O.k. We aren't just an intermediary anymore!
 117 ####
 118 ###
 119 ### Romcc output
 120 ###
 121 makerule ./failover.E
 122         depends "$(MAINBOARD)/failover.c"
 123         action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
 124 end
 125
 126 makerule ./failover.inc
 127         depends "./romcc ./failover.E"
 128         action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
 129 end
 130
 131 makerule ./auto.E
 132         depends "$(MAINBOARD)/auto.c option_table.h"
 133         action  "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
 134 end
 135
 136 makerule ./auto.inc
 137         depends "./romcc ./auto.E"
 138         action "./romcc -O2 -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E"
 139 end
 140
 141 mainboardinit cpu/k8/enable_mmx_sse.inc
 142 mainboardinit ./auto.inc
 143 mainboardinit cpu/k8/disable_mmx_sse.inc
 144
 145 #
 146 ###
 147 ### Include the secondary Configuration files
 148 ###
 149 dir /pc80
 150
 151 northbridge amd/amdk8 "mc0"
 152         pci 0:18.0
 153         pci 0:18.0
 154         pci 0:18.0
 155         pci 0:18.1
 156         pci 0:18.2
 157         pci 0:18.3
 158         southbridge amd/amd8151 "amd8151" link 0
 159                 pci 0:0.0
 160                 pci 0:1.0
 161         end
 162         southbridge amd/amd8111 "amd8111" link 0
 163                 pci 0:0.0
 164                 pci 0:1.0 on
 165                 pci 0:1.1 on
 166                 pci 0:1.2 on
 167                 pci 0:1.3 on
 168                 pci 0:1.5 on
 169                 pci 0:1.6 off
 170                 pci 1:0.0 on
 171                 pci 1:0.1 on
 172                 pci 1:0.2 on
 173                 pci 1:1.0 off
 174                 superio winbond/w83627hf link 1
 175                         pnp 2e.0 on #  Floppy
 176                                  io 0x60 = 0x3f0
 177                                 irq 0x70 = 6
 178                                 drq 0x74 = 2
 179                         pnp 2e.1 off #  Parallel Port
 180                                  io 0x60 = 0x378
 181                                 irq 0x70 = 7
 182                         pnp 2e.2 on #  Com1
 183                                  io 0x60 = 0x3f8
 184                                 irq 0x70 = 4
 185                         pnp 2e.3 off #  Com2
 186                                  io 0x60 = 0x2f8
 187                                 irq 0x70 = 3
 188                         pnp 2e.5 on #  Keyboard
 189                                  io 0x60 = 0x60
 190                                  io 0x62 = 0x64
 191                                 irq 0x70 = 1
 192                                 irq 0x72 = 12
 193                         pnp 2e.6 off #  CIR
 194                         pnp 2e.7 off #  GAME_MIDI_GIPO1
 195                         pnp 2e.8 off #  GPIO2
 196                         pnp 2e.9 off #  GPIO3
 197                         pnp 2e.a off #  ACPI
 198                         pnp 2e.b on #  HW Monitor
 199                                  io 0x60 = 0x290
 200                 end
 201         end
 202 end
 203
 204 northbridge amd/amdk8 "mc1"
 205         pci 0:19.0
 206         pci 0:19.0
 207         pci 0:19.0
 208         pci 0:19.1
 209         pci 0:19.2
 210         pci 0:19.3
 211 end
 212
 213 #dir /bioscall
 214
 215 cpu k8 "cpu0"
 216   register "up" = "{.chip = &amd8151, .ht_width=16, .ht_speed=600}"
 217 end
 218
 219 cpu k8 "cpu1"
 220 end
 221