src/mainboard/tyan/s2850/romstage.c

   1 #include <stdint.h>
   2 #include <string.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <stdlib.h>
   8 #include <pc80/mc146818rtc.h>
   9 #include <console/console.h>
  10 #include <lib.h>
  11 #include <spd.h>
  12 #include <cpu/amd/model_fxx_rev.h>
  13 #include "northbridge/amd/amdk8/incoherent_ht.c"
  14 #include "southbridge/amd/amd8111/early_smbus.c"
  15 #include "northbridge/amd/amdk8/raminit.h"
  16 #include "cpu/amd/model_fxx/apic_timer.c"
  17 #include "lib/delay.c"
  18 #include "northbridge/amd/amdk8/reset_test.c"
  19 #include "northbridge/amd/amdk8/debug.c"
  20 #include "superio/winbond/w83627hf/early_serial.c"
  21 #include "cpu/x86/mtrr/earlymtrr.c"
  22 #include "cpu/x86/bist.h"
  23 #include "northbridge/amd/amdk8/setup_resource_map.c"
  24 #include "southbridge/amd/amd8111/early_ctrl.c"
  25
  26 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  27
  28 static void memreset_setup(void)
  29 {
  30    if (is_cpu_pre_c0())
  31         outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  32    else
  33         outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  34    outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  35 }
  36
  37 static void memreset(int controllers, const struct mem_controller *ctrl)
  38 {
  39    if (is_cpu_pre_c0()) {
  40         udelay(800);
  41         outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  42         udelay(90);
  43    }
  44 }
  45
  46 static void activate_spd_rom(const struct mem_controller *ctrl) { }
  47
  48 static inline int spd_read_byte(unsigned device, unsigned address)
  49 {
  50         return smbus_read_byte(device, address);
  51 }
  52
  53 #include "northbridge/amd/amdk8/raminit.c"
  54 #include "northbridge/amd/amdk8/resourcemap.c"
  55 #include "northbridge/amd/amdk8/coherent_ht.c"
  56 #include "lib/generic_sdram.c"
  57 #include "cpu/amd/dualcore/dualcore.c"
  58 #include "cpu/amd/car/post_cache_as_ram.c"
  59 #include "cpu/amd/model_fxx/init_cpus.c"
  60
  61 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  62 {
  63         static const struct mem_controller cpu[] = {
  64                 {
  65                         .node_id = 0,
  66                         .f0 = PCI_DEV(0, 0x18, 0),
  67                         .f1 = PCI_DEV(0, 0x18, 1),
  68                         .f2 = PCI_DEV(0, 0x18, 2),
  69                         .f3 = PCI_DEV(0, 0x18, 3),
  70                         .channel0 = { DIMM0, DIMM2, 0, 0 },
  71                         .channel1 = { DIMM1, DIMM3, 0, 0 },
  72                 },
  73         };
  74
  75         int needs_reset;
  76
  77         if (bist == 0)
  78                 init_cpus(cpu_init_detectedx);
  79
  80 //      post_code(0x32);
  81
  82         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  83         console_init();
  84
  85         /* Halt if there was a built in self test failure */
  86         report_bist_failure(bist);
  87
  88         setup_default_resource_map();
  89
  90         needs_reset = setup_coherent_ht_domain();
  91
  92 #if CONFIG_LOGICAL_CPUS==1
  93         // It is said that we should start core1 after all core0 launched
  94         start_other_cores();
  95 #endif
  96         needs_reset |= ht_setup_chains_x();
  97
  98         if (needs_reset) {
  99                 print_info("ht reset -\n");
 100                 soft_reset();
 101         }
 102
 103         enable_smbus();
 104
 105         memreset_setup();
 106         sdram_initialize(ARRAY_SIZE(cpu), cpu);
 107
 108         post_cache_as_ram();
 109 }