4 #include <device/pci_def.h>
6 #include <device/pnp_def.h>
7 #include <arch/romcc_io.h>
8 #include <cpu/x86/lapic.h>
10 #include "option_table.h"
11 #include "pc80/mc146818rtc_early.c"
12 #include "pc80/serial.c"
13 #include "console/console.c"
14 #include "lib/ramtest.c"
17 static void post_code(uint8_t value) {
20 for(i=0;i<0x80000;i++) {
27 #include <cpu/amd/model_fxx_rev.h>
28 #include "northbridge/amd/amdk8/incoherent_ht.c"
29 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
30 #include "northbridge/amd/amdk8/raminit.h"
31 #include "cpu/amd/model_fxx/apic_timer.c"
32 #include "lib/delay.c"
34 #include "cpu/x86/lapic/boot_cpu.c"
35 #include "northbridge/amd/amdk8/reset_test.c"
36 #include "northbridge/amd/amdk8/debug.c"
37 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
39 #include "cpu/amd/mtrr/amd_earlymtrr.c"
40 #include "cpu/x86/bist.h"
42 #include "northbridge/amd/amdk8/setup_resource_map.c"
44 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
46 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
48 static void memreset_setup(void)
50 if (is_cpu_pre_c0()) {
51 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
54 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
56 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
59 static void memreset(int controllers, const struct mem_controller *ctrl)
61 if (is_cpu_pre_c0()) {
63 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
68 static inline void activate_spd_rom(const struct mem_controller *ctrl)
73 static inline int spd_read_byte(unsigned device, unsigned address)
75 return smbus_read_byte(device, address);
78 #include "northbridge/amd/amdk8/raminit.c"
79 #include "northbridge/amd/amdk8/resourcemap.c"
80 #include "northbridge/amd/amdk8/coherent_ht.c"
81 #include "lib/generic_sdram.c"
83 #if CONFIG_LOGICAL_CPUS==1
84 #define SET_NB_CFG_54 1
86 #include "cpu/amd/dualcore/dualcore.c"
88 #include "cpu/amd/car/copy_and_run.c"
90 #include "cpu/amd/car/post_cache_as_ram.c"
92 #include "cpu/amd/model_fxx/init_cpus.c"
94 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
95 #include "northbridge/amd/amdk8/early_ht.c"
97 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
99 static const struct mem_controller cpu[] = {
102 .f0 = PCI_DEV(0, 0x18, 0),
103 .f1 = PCI_DEV(0, 0x18, 1),
104 .f2 = PCI_DEV(0, 0x18, 2),
105 .f3 = PCI_DEV(0, 0x18, 3),
106 .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
107 .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
113 if (!cpu_init_detectedx && boot_cpu()) {
114 /* Nothing special needs to be done to find bus 0 */
115 /* Allow the HT devices to be found */
117 enumerate_ht_chain();
119 /* Setup the amd8111 */
120 amd8111_enable_rom();
124 init_cpus(cpu_init_detectedx);
129 w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
133 /* Halt if there was a built in self test failure */
134 report_bist_failure(bist);
136 setup_default_resource_map();
138 needs_reset = setup_coherent_ht_domain();
140 #if CONFIG_LOGICAL_CPUS==1
141 // It is said that we should start core1 after all core0 launched
144 needs_reset |= ht_setup_chains_x();
147 print_info("ht reset -\n");
154 sdram_initialize(ARRAY_SIZE(cpu), cpu);