src/mainboard/tyan/s2850/romstage.c

   1 #define ASSEMBLY 1
   2 #define __PRE_RAM__
   3
   4 #include <stdint.h>
   5 #include <string.h>
   6 #include <device/pci_def.h>
   7 #include <arch/io.h>
   8 #include <device/pnp_def.h>
   9 #include <arch/romcc_io.h>
  10 #include <cpu/x86/lapic.h>
  11 #include <stdlib.h>
  12 #include "option_table.h"
  13 #include "pc80/mc146818rtc_early.c"
  14 #include "pc80/serial.c"
  15 #include "arch/i386/lib/console.c"
  16 #include "lib/ramtest.c"
  17
  18 #if 0
  19 static void post_code(uint8_t value) {
  20 #if 1
  21         int i;
  22         for(i=0;i<0x80000;i++) {
  23                 outb(value, 0x80);
  24         }
  25 #endif
  26 }
  27 #endif
  28
  29 #include <cpu/amd/model_fxx_rev.h>
  30 #include "northbridge/amd/amdk8/incoherent_ht.c"
  31 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  32 #include "northbridge/amd/amdk8/raminit.h"
  33 #include "cpu/amd/model_fxx/apic_timer.c"
  34 #include "lib/delay.c"
  35
  36 #include "cpu/x86/lapic/boot_cpu.c"
  37 #include "northbridge/amd/amdk8/reset_test.c"
  38 #include "northbridge/amd/amdk8/debug.c"
  39 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  40
  41 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  42 #include "cpu/x86/bist.h"
  43
  44 #include "northbridge/amd/amdk8/setup_resource_map.c"
  45
  46 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  47
  48 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  49
  50 static void memreset_setup(void)
  51 {
  52    if (is_cpu_pre_c0()) {
  53         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  54    }
  55    else {
  56         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  57    }
  58         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  59 }
  60
  61 static void memreset(int controllers, const struct mem_controller *ctrl)
  62 {
  63    if (is_cpu_pre_c0()) {
  64         udelay(800);
  65         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  66         udelay(90);
  67    }
  68 }
  69
  70 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  71 {
  72         /* nothing to do */
  73 }
  74
  75 static inline int spd_read_byte(unsigned device, unsigned address)
  76 {
  77         return smbus_read_byte(device, address);
  78 }
  79
  80 #include "northbridge/amd/amdk8/raminit.c"
  81 #include "northbridge/amd/amdk8/resourcemap.c"
  82 #include "northbridge/amd/amdk8/coherent_ht.c"
  83 #include "lib/generic_sdram.c"
  84
  85 #if CONFIG_LOGICAL_CPUS==1
  86 #define SET_NB_CFG_54 1
  87 #endif
  88 #include "cpu/amd/dualcore/dualcore.c"
  89
  90 #include "cpu/amd/car/copy_and_run.c"
  91
  92 #include "cpu/amd/car/post_cache_as_ram.c"
  93
  94 #include "cpu/amd/model_fxx/init_cpus.c"
  95
  96
  97 #if CONFIG_USE_FALLBACK_IMAGE == 1
  98
  99 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 100 #include "northbridge/amd/amdk8/early_ht.c"
 101
 102 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 103 {
 104         unsigned last_boot_normal_x = last_boot_normal();
 105
 106         /* Is this a cpu only reset? or Is this a secondary cpu? */
 107         if ((cpu_init_detectedx) || (!boot_cpu())) {
 108                 if (last_boot_normal_x) {
 109                         goto normal_image;
 110                 } else {
 111                         goto fallback_image;
 112                 }
 113         }
 114
 115         /* Nothing special needs to be done to find bus 0 */
 116         /* Allow the HT devices to be found */
 117
 118         enumerate_ht_chain();
 119
 120         /* Setup the amd8111 */
 121         amd8111_enable_rom();
 122
 123         /* Is this a deliberate reset by the bios */
 124 //        post_code(0x22);
 125         if (bios_reset_detected() && last_boot_normal_x) {
 126                 goto normal_image;
 127         }
 128         /* This is the primary cpu how should I boot? */
 129         else if (do_normal_boot()) {
 130                 goto normal_image;
 131         }
 132         else {
 133                 goto fallback_image;
 134         }
 135  normal_image:
 136 //        post_code(0x23);
 137         __asm__ volatile ("jmp __normal_image"
 138                 : /* outputs */
 139                 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
 140                 );
 141
 142  fallback_image:
 143 //        post_code(0x25);
 144         ;
 145 }
 146 #endif
 147
 148 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 149
 150 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 151 {
 152
 153 #if CONFIG_USE_FALLBACK_IMAGE == 1
 154         failover_process(bist, cpu_init_detectedx);
 155 #endif
 156         real_main(bist, cpu_init_detectedx);
 157
 158 }
 159
 160 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 161 {
 162         static const struct mem_controller cpu[] = {
 163                 {
 164                         .node_id = 0,
 165                         .f0 = PCI_DEV(0, 0x18, 0),
 166                         .f1 = PCI_DEV(0, 0x18, 1),
 167                         .f2 = PCI_DEV(0, 0x18, 2),
 168                         .f3 = PCI_DEV(0, 0x18, 3),
 169                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 170                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 171                 },
 172         };
 173
 174         int needs_reset;
 175
 176         if (bist == 0) {
 177                 init_cpus(cpu_init_detectedx);
 178         }
 179
 180 //      post_code(0x32);
 181
 182         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 183         uart_init();
 184         console_init();
 185
 186         /* Halt if there was a built in self test failure */
 187         report_bist_failure(bist);
 188
 189         setup_default_resource_map();
 190
 191         needs_reset = setup_coherent_ht_domain();
 192
 193 #if CONFIG_LOGICAL_CPUS==1
 194         // It is said that we should start core1 after all core0 launched
 195         start_other_cores();
 196 #endif
 197         needs_reset |= ht_setup_chains_x();
 198
 199         if (needs_reset) {
 200                 print_info("ht reset -\r\n");
 201                 soft_reset();
 202         }
 203
 204         enable_smbus();
 205
 206         memreset_setup();
 207         sdram_initialize(ARRAY_SIZE(cpu), cpu);
 208
 209         post_cache_as_ram();
 210 }