src/mainboard/tyan/s2850/cache_as_ram_auto.c

   1 #define ASSEMBLY 1
   2 #define __ROMCC__
   3
   4 #include <stdint.h>
   5 #include <device/pci_def.h>
   6 #include <arch/io.h>
   7 #include <device/pnp_def.h>
   8 #include <arch/romcc_io.h>
   9 #include <cpu/x86/lapic.h>
  10 #include "option_table.h"
  11 #include "pc80/mc146818rtc_early.c"
  12 #include "pc80/serial.c"
  13 #include "arch/i386/lib/console.c"
  14 #include "ram/ramtest.c"
  15
  16 #if 0
  17 static void post_code(uint8_t value) {
  18 #if 1
  19         int i;
  20         for(i=0;i<0x80000;i++) {
  21                 outb(value, 0x80);
  22         }
  23 #endif
  24 }
  25 #endif
  26
  27 #include <cpu/amd/model_fxx_rev.h>
  28 #include "northbridge/amd/amdk8/incoherent_ht.c"
  29 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  30 #include "northbridge/amd/amdk8/raminit.h"
  31 #include "cpu/amd/model_fxx/apic_timer.c"
  32 #include "lib/delay.c"
  33
  34 #if CONFIG_USE_INIT == 0
  35 #include "lib/memcpy.c"
  36 #endif
  37
  38 #include "cpu/x86/lapic/boot_cpu.c"
  39 #include "northbridge/amd/amdk8/reset_test.c"
  40 #include "northbridge/amd/amdk8/debug.c"
  41 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  42
  43 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  44 #include "cpu/x86/bist.h"
  45
  46 #include "northbridge/amd/amdk8/setup_resource_map.c"
  47
  48 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  49
  50 static void hard_reset(void)
  51 {
  52         device_t dev;
  53
  54         /* Find the device */
  55         dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3);
  56
  57         set_bios_reset();
  58
  59         /* enable cf9 */
  60         pci_write_config8(dev, 0x41, 0xf1);
  61         /* reset */
  62         outb(0x0e, 0x0cf9);
  63 }
  64
  65 static void soft_reset(void)
  66 {
  67         device_t dev;
  68
  69         /* Find the device */
  70         dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0);
  71
  72         set_bios_reset();
  73         pci_write_config8(dev, 0x47, 1);
  74 }
  75
  76 static void memreset_setup(void)
  77 {
  78    if (is_cpu_pre_c0()) {
  79         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  80    }
  81    else {
  82         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  83    }
  84         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  85 }
  86
  87 static void memreset(int controllers, const struct mem_controller *ctrl)
  88 {
  89    if (is_cpu_pre_c0()) {
  90         udelay(800);
  91         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  92         udelay(90);
  93    }
  94 }
  95
  96 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  97 {
  98         /* nothing to do */
  99 }
 100
 101 static inline int spd_read_byte(unsigned device, unsigned address)
 102 {
 103         return smbus_read_byte(device, address);
 104 }
 105
 106 #define K8_4RANK_DIMM_SUPPORT 1
 107
 108 #include "northbridge/amd/amdk8/raminit.c"
 109 #include "northbridge/amd/amdk8/resourcemap.c"
 110 #include "northbridge/amd/amdk8/coherent_ht.c"
 111 #include "sdram/generic_sdram.c"
 112
 113 #if CONFIG_LOGICAL_CPUS==1
 114 #define SET_NB_CFG_54 1
 115 #endif
 116 #include "cpu/amd/dualcore/dualcore.c"
 117
 118 #include "cpu/amd/car/copy_and_run.c"
 119
 120 #include "cpu/amd/car/post_cache_as_ram.c"
 121
 122 #include "cpu/amd/model_fxx/init_cpus.c"
 123
 124
 125 #if USE_FALLBACK_IMAGE == 1
 126
 127 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 128 #include "northbridge/amd/amdk8/early_ht.c"
 129
 130 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 131 {
 132         unsigned last_boot_normal_x = last_boot_normal();
 133
 134         /* Is this a cpu only reset? or Is this a secondary cpu? */
 135         if ((cpu_init_detectedx) || (!boot_cpu())) {
 136                 if (last_boot_normal_x) {
 137                         goto normal_image;
 138                 } else {
 139                         goto fallback_image;
 140                 }
 141         }
 142
 143         /* Nothing special needs to be done to find bus 0 */
 144         /* Allow the HT devices to be found */
 145
 146         enumerate_ht_chain();
 147
 148         /* Setup the amd8111 */
 149         amd8111_enable_rom();
 150
 151         /* Is this a deliberate reset by the bios */
 152 //        post_code(0x22);
 153         if (bios_reset_detected() && last_boot_normal_x) {
 154                 goto normal_image;
 155         }
 156         /* This is the primary cpu how should I boot? */
 157         else if (do_normal_boot()) {
 158                 goto normal_image;
 159         }
 160         else {
 161                 goto fallback_image;
 162         }
 163  normal_image:
 164 //        post_code(0x23);
 165         __asm__ volatile ("jmp __normal_image"
 166                 : /* outputs */
 167                 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
 168                 );
 169
 170  fallback_image:
 171 //        post_code(0x25);
 172         ;
 173 }
 174 #endif
 175
 176 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 177
 178 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 179 {
 180
 181 #if USE_FALLBACK_IMAGE == 1
 182         failover_process(bist, cpu_init_detectedx);
 183 #endif
 184         real_main(bist, cpu_init_detectedx);
 185
 186 }
 187
 188 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 189 {
 190         static const struct mem_controller cpu[] = {
 191                 {
 192                         .node_id = 0,
 193                         .f0 = PCI_DEV(0, 0x18, 0),
 194                         .f1 = PCI_DEV(0, 0x18, 1),
 195                         .f2 = PCI_DEV(0, 0x18, 2),
 196                         .f3 = PCI_DEV(0, 0x18, 3),
 197                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 198                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 199                 },
 200         };
 201
 202         int needs_reset;
 203         unsigned cpu_reset = 0;
 204
 205         if (bist == 0) {
 206                 init_cpus(cpu_init_detectedx);
 207         }
 208
 209 //      post_code(0x32);
 210
 211         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 212         uart_init();
 213         console_init();
 214
 215         /* Halt if there was a built in self test failure */
 216         report_bist_failure(bist);
 217
 218         setup_default_resource_map();
 219
 220         needs_reset = setup_coherent_ht_domain();
 221
 222 #if CONFIG_LOGICAL_CPUS==1
 223         // It is said that we should start core1 after all core0 launched
 224         start_other_cores();
 225 #endif
 226         needs_reset |= ht_setup_chains_x();
 227
 228         if (needs_reset) {
 229                 print_info("ht reset -\r\n");
 230                 soft_reset();
 231         }
 232
 233         enable_smbus();
 234
 235         memreset_setup();
 236         sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 237
 238         post_cache_as_ram(cpu_reset);
 239 }