2 ## Compute the location and size of where this firmware image
3 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
6 default ROM_SECTION_SIZE = FALLBACK_SIZE
7 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
9 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
10 default ROM_SECTION_OFFSET = 0
14 ## Compute the start location and size size of
15 ## The linuxBIOS bootloader.
17 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
18 default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
21 ## Compute where this copy of linuxBIOS will start in the boot rom
23 default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
26 ## Compute a range of ROM that can cached to speed up linuxBIOS,
29 ## XIP_ROM_SIZE must be a power of 2.
30 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
32 default XIP_ROM_SIZE=65536
33 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
38 ## Build the objects we have code for in this directory.
45 if HAVE_MP_TABLE object mptable.o end
46 if HAVE_PIRQ_TABLE object irq_tables.o end
54 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
55 action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
61 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
62 action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
63 action "perl -e 's/.rodata/.rom.data/g' -pi $@"
64 action "perl -e 's/.text/.section .rom.text/g' -pi $@"
74 depends "$(MAINBOARD)/failover.c ./romcc"
75 action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
78 makerule ./failover.inc
79 depends "$(MAINBOARD)/failover.c ./romcc"
80 action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
84 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
85 action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
88 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
89 action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
94 ## Build our 16 bit and 32 bit linuxBIOS entry code
97 mainboardinit cpu/x86/16bit/entry16.inc
98 ldscript /cpu/x86/16bit/entry16.lds
101 mainboardinit cpu/x86/32bit/entry32.inc
105 ldscript /cpu/x86/32bit/entry32.lds
109 ldscript /cpu/amd/car/cache_as_ram.lds
114 ## Build our reset vector (This is where linuxBIOS is entered)
116 if USE_FALLBACK_IMAGE
117 mainboardinit cpu/x86/16bit/reset16.inc
118 ldscript /cpu/x86/16bit/reset16.lds
120 mainboardinit cpu/x86/32bit/reset32.inc
121 ldscript /cpu/x86/32bit/reset32.lds
126 ### Should this be in the northbridge code?
127 mainboardinit arch/i386/lib/cpu_reset.inc
131 ## Include an id string (For safe flashing)
133 mainboardinit arch/i386/lib/id.inc
134 ldscript /arch/i386/lib/id.lds
138 ## Setup Cache-As-Ram
140 mainboardinit cpu/amd/car/cache_as_ram.inc
144 ### This is the early phase of linuxBIOS startup
145 ### Things are delicate and we test to see if we should
146 ### failover to another image.
148 if USE_FALLBACK_IMAGE
150 ldscript /arch/i386/lib/failover.lds
152 ldscript /arch/i386/lib/failover.lds
153 mainboardinit ./failover.inc
158 ### O.k. We aren't just an intermediary anymore!
169 mainboardinit ./auto.inc
177 mainboardinit cpu/x86/fpu/enable_fpu.inc
178 mainboardinit cpu/x86/mmx/enable_mmx.inc
179 mainboardinit cpu/x86/sse/enable_sse.inc
180 mainboardinit ./auto.inc
181 mainboardinit cpu/x86/sse/disable_sse.inc
182 mainboardinit cpu/x86/mmx/disable_mmx.inc
187 ## Include the secondary Configuration files
193 # sample config for tyan/s2850
194 chip northbridge/amd/amdk8/root_complex
195 device apic_cluster 0 on
196 chip cpu/amd/socket_940
200 device pci_domain 0 on
201 chip northbridge/amd/amdk8
202 device pci 18.0 on # LDT0
203 # devices on link 2, link 2 == LDT 2
204 chip southbridge/amd/amd8111
205 # this "device pci 0.0" is the parent the next one
208 device pci 0.0 on end
209 device pci 0.1 on end
210 device pci 0.2 off end
211 device pci 1.0 off end
212 #chip drivers/ati/ragexl
213 chip drivers/pci/onboard
214 device pci b.0 on end
215 register "rom_address" = "0xfff80000"
219 chip superio/winbond/w83627hf
220 device pnp 2e.0 on # Floppy
225 device pnp 2e.1 off # Parallel Port
229 device pnp 2e.2 on # Com1
233 device pnp 2e.3 off # Com2
237 device pnp 2e.5 on # Keyboard
243 device pnp 2e.6 off # CIR
246 device pnp 2e.7 off # GAME_MIDI_GIPO1
251 device pnp 2e.8 off end # GPIO2
252 device pnp 2e.9 off end # GPIO3
253 device pnp 2e.a off end # ACPI
254 device pnp 2e.b on # HW Monitor
260 device pci 1.1 on end
261 device pci 1.2 on end
263 chip drivers/generic/generic #dimm 0-0-0
266 chip drivers/generic/generic #dimm 0-0-1
269 chip drivers/generic/generic #dimm 0-1-0
272 chip drivers/generic/generic #dimm 0-1-1
276 device pci 1.5 on end
277 device pci 1.6 off end
278 register "ide0_enable" = "1"
279 register "ide1_enable" = "1"
281 end # device pci 18.0
282 device pci 18.0 on end
283 device pci 18.0 on end
285 device pci 18.1 on end
286 device pci 18.2 on end
287 device pci 18.3 on end