1 include /config/nofailovercalculation.lb
6 ## Build the objects we have code for in this directory.
13 if HAVE_MP_TABLE object mptable.o end
14 if HAVE_PIRQ_TABLE object irq_tables.o end
19 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
20 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
26 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
27 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
28 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
29 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
34 ## Build our 16 bit and 32 bit coreboot entry code
37 mainboardinit cpu/x86/16bit/entry16.inc
38 ldscript /cpu/x86/16bit/entry16.lds
41 mainboardinit cpu/x86/32bit/entry32.inc
44 ldscript /cpu/x86/32bit/entry32.lds
48 ldscript /cpu/amd/car/cache_as_ram.lds
52 ## Build our reset vector (This is where coreboot is entered)
55 mainboardinit cpu/x86/16bit/reset16.inc
56 ldscript /cpu/x86/16bit/reset16.lds
58 mainboardinit cpu/x86/32bit/reset32.inc
59 ldscript /cpu/x86/32bit/reset32.lds
63 ## Include an id string (For safe flashing)
65 mainboardinit arch/i386/lib/id.inc
66 ldscript /arch/i386/lib/id.lds
71 mainboardinit cpu/amd/car/cache_as_ram.inc
74 ### This is the early phase of coreboot startup
75 ### Things are delicate and we test to see if we should
76 ### failover to another image.
79 ldscript /arch/i386/lib/failover.lds
83 ### O.k. We aren't just an intermediary anymore!
92 mainboardinit ./auto.inc
96 ## Include the secondary Configuration files
100 # sample config for tyan/s2850
101 chip northbridge/amd/amdk8/root_complex
102 device apic_cluster 0 on
103 chip cpu/amd/socket_940
107 device pci_domain 0 on
108 chip northbridge/amd/amdk8
109 device pci 18.0 on # LDT0
110 # devices on link 2, link 2 == LDT 2
111 chip southbridge/amd/amd8111
112 # this "device pci 0.0" is the parent the next one
115 device pci 0.0 on end
116 device pci 0.1 on end
117 device pci 0.2 off end
118 device pci 1.0 off end
119 #chip drivers/ati/ragexl
120 chip drivers/pci/onboard
121 device pci b.0 on end
122 register "rom_address" = "0xfff80000"
126 chip superio/winbond/w83627hf
127 device pnp 2e.0 on # Floppy
132 device pnp 2e.1 off # Parallel Port
136 device pnp 2e.2 on # Com1
140 device pnp 2e.3 off # Com2
144 device pnp 2e.5 on # Keyboard
150 device pnp 2e.6 off # CIR
153 device pnp 2e.7 off # GAME_MIDI_GIPO1
158 device pnp 2e.8 off end # GPIO2
159 device pnp 2e.9 off end # GPIO3
160 device pnp 2e.a off end # ACPI
161 device pnp 2e.b on # HW Monitor
167 device pci 1.1 on end
168 device pci 1.2 on end
170 chip drivers/generic/generic #dimm 0-0-0
173 chip drivers/generic/generic #dimm 0-0-1
176 chip drivers/generic/generic #dimm 0-1-0
179 chip drivers/generic/generic #dimm 0-1-1
183 device pci 1.5 on end
184 device pci 1.6 off end
185 register "ide0_enable" = "1"
186 register "ide1_enable" = "1"
188 end # device pci 18.0
189 device pci 18.0 on end
190 device pci 18.0 on end
192 device pci 18.1 on end
193 device pci 18.2 on end
194 device pci 18.3 on end