src/mainboard/tyan/s2850/Config.lb

   1 ##
   2 ## Compute the location and size of where this firmware image
   3 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
   4 ##
   5 if USE_FALLBACK_IMAGE
   6         default ROM_SECTION_SIZE   = FALLBACK_SIZE
   7         default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
   8 else
   9         default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
  10         default ROM_SECTION_OFFSET = 0
  11 end
  12
  13 ##
  14 ## Compute the start location and size size of
  15 ## The linuxBIOS bootloader.
  16 ##
  17 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
  18 default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
  19
  20 ##
  21 ## Compute where this copy of linuxBIOS will start in the boot rom
  22 ##
  23 default _ROMBASE      = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
  24
  25 ##
  26 ## Compute a range of ROM that can cached to speed up linuxBIOS,
  27 ## execution speed.
  28 ##
  29 ## XIP_ROM_SIZE must be a power of 2.
  30 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
  31 ##
  32 default XIP_ROM_SIZE=65536
  33 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
  34
  35 arch i386 end
  36
  37 ##
  38 ## Build the objects we have code for in this directory.
  39 ##
  40
  41 driver mainboard.o
  42 if HAVE_MP_TABLE object mptable.o end
  43 if HAVE_PIRQ_TABLE object irq_tables.o end
  44 #object reset.o
  45
  46 ##
  47 ## Romcc output
  48 ##
  49 makerule ./failover.E
  50         depends "$(MAINBOARD)/failover.c ./romcc"
  51         action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
  52 end
  53
  54 makerule ./failover.inc
  55         depends "$(MAINBOARD)/failover.c ./romcc"
  56         action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
  57 end
  58
  59 makerule ./auto.E
  60         depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
  61         action  "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
  62 end
  63 makerule ./auto.inc
  64         depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
  65         action  "./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
  66 end
  67
  68 ##
  69 ## Build our 16 bit and 32 bit linuxBIOS entry code
  70 ##
  71 mainboardinit cpu/x86/16bit/entry16.inc
  72 mainboardinit cpu/x86/32bit/entry32.inc
  73 ldscript /cpu/x86/16bit/entry16.lds
  74 ldscript /cpu/x86/32bit/entry32.lds
  75
  76 ##
  77 ## Build our reset vector (This is where linuxBIOS is entered)
  78 ##
  79 if USE_FALLBACK_IMAGE
  80         mainboardinit cpu/x86/16bit/reset16.inc
  81         ldscript /cpu/x86/16bit/reset16.lds
  82 else
  83         mainboardinit cpu/x86/32bit/reset32.inc
  84         ldscript /cpu/x86/32bit/reset32.lds
  85 end
  86
  87 ### Should this be in the northbridge code?
  88 mainboardinit arch/i386/lib/cpu_reset.inc
  89
  90 ##
  91 ## Include an id string (For safe flashing)
  92 ##
  93 mainboardinit arch/i386/lib/id.inc
  94 ldscript /arch/i386/lib/id.lds
  95
  96 ###
  97 ### This is the early phase of linuxBIOS startup
  98 ### Things are delicate and we test to see if we should
  99 ### failover to another image.
 100 ###
 101 if USE_FALLBACK_IMAGE
 102         ldscript /arch/i386/lib/failover.lds
 103         mainboardinit ./failover.inc
 104 end
 105
 106 ###
 107 ### O.k. We aren't just an intermediary anymore!
 108 ###
 109
 110 ##
 111 ## Setup RAM
 112 ##
 113 mainboardinit cpu/x86/fpu/enable_fpu.inc
 114 mainboardinit cpu/x86/mmx/enable_mmx.inc
 115 mainboardinit cpu/x86/sse/enable_sse.inc
 116 mainboardinit ./auto.inc
 117 mainboardinit cpu/x86/sse/disable_sse.inc
 118 mainboardinit cpu/x86/mmx/disable_mmx.inc
 119
 120 ##
 121 ## Include the secondary Configuration files
 122 ##
 123 dir /pc80
 124 if CONFIG_CHIP_NAME
 125         config chip.h
 126 end
 127
 128 # sample config for tyan/s2850
 129 chip northbridge/amd/amdk8/root_complex
 130         device pci_domain 0 on
 131                 chip northbridge/amd/amdk8
 132                         device pci 18.0 on # LDT0
 133                                 #  devices on link 2, link 2 == LDT 2
 134                                 chip southbridge/amd/amd8111
 135                                         # this "device pci 0.0" is the parent the next one
 136                                         # PCI bridge
 137                                         device pci 0.0 on
 138                                                 device pci 0.0 on end
 139                                                 device pci 0.1 on end
 140                                                 device pci 0.2 off end
 141                                                 device pci 1.0 off end
 142                                         end
 143                                         device pci 1.0 on
 144                                                 chip superio/winbond/w83627hf
 145                                                         device pnp 2e.0 on #  Floppy
 146                                                                 io 0x60 = 0x3f0
 147                                                                 irq 0x70 = 6
 148                                                                 drq 0x74 = 2
 149                                                         end
 150                                                         device pnp 2e.1 off #  Parallel Port
 151                                                                 io 0x60 = 0x378
 152                                                                 irq 0x70 = 7
 153                                                         end
 154                                                         device pnp 2e.2 on #  Com1
 155                                                                 io 0x60 = 0x3f8
 156                                                                 irq 0x70 = 4
 157                                                         end
 158                                                         device pnp 2e.3 off #  Com2
 159                                                                 io 0x60 = 0x2f8
 160                                                                 irq 0x70 = 3
 161                                                         end
 162                                                         device pnp 2e.5 on #  Keyboard
 163                                                                 io 0x60 = 0x60
 164                                                                 io 0x62 = 0x64
 165                                                                 irq 0x70 = 1
 166                                                                 irq 0x72 = 12
 167                                                         end
 168                                                        device pnp 2e.6 off #  CIR
 169                                                                 io 0x60 = 0x100
 170                                                         end
 171                                                         device pnp 2e.7 off #  GAME_MIDI_GIPO1
 172                                                                 io 0x60 = 0x201
 173                                                                 io 0x62 = 0x330
 174                                                                 irq 0x70 = 9
 175                                                         end
 176                                                         device pnp 2e.8 off end #  GPIO2
 177                                                         device pnp 2e.9 off end #  GPIO3
 178                                                         device pnp 2e.a off end #  ACPI
 179                                                         device pnp 2e.b on #  HW Monitor
 180                                                                 io 0x60 = 0x290
 181                                                                 irq 0x70 = 5
 182                                                         end
 183                                                 end
 184                                         end
 185                                         device pci 1.1 on end
 186                                         device pci 1.2 on end
 187                                         device pci 1.3 on end
 188                                         device pci 1.5 on end
 189                                         device pci 1.6 off end
 190                                 end
 191                         end #  device pci 18.0
 192                         device pci 18.0 on end
 193                         device pci 18.0 on end
 194
 195                         device pci 18.1 on end
 196                         device pci 18.2 on end
 197                         device pci 18.3 on end
 198                 end
 199         end
 200         device apic_cluster 0 on
 201                 chip cpu/amd/socket_940
 202                         device apic 0 on end
 203                 end
 204         end
 205 end
 206