3 uses USE_FALLBACK_IMAGE
8 uses HARD_RESET_FUNCTION
12 ### Set all of the defaults for an x86 architecture
17 ### Build the objects we have code for in this directory.
21 register "fixup_scsi" = "1"
22 register "fixup_vga" = "1"
31 #object static_devices.o
32 if HAVE_MP_TABLE object mptable.o end
33 if HAVE_PIRQ_TABLE object irq_tables.o end
35 default HARD_RESET_BUS=1
36 default HARD_RESET_DEVICE=2
37 default HARD_RESET_FUNCTION=0
43 ### Build our 16 bit and 32 bit linuxBIOS entry code
45 mainboardinit cpu/i386/entry16.inc
46 mainboardinit cpu/i386/entry32.inc
47 ldscript /cpu/i386/entry16.lds
48 ldscript /cpu/i386/entry32.lds
51 ### Build our reset vector (This is where linuxBIOS is entered)
54 mainboardinit cpu/i386/reset16.inc
55 ldscript /cpu/i386/reset16.lds
57 mainboardinit cpu/i386/reset32.inc
58 ldscript /cpu/i386/reset32.lds
61 #### Should this be in the northbridge code?
62 mainboardinit arch/i386/lib/cpu_reset.inc
65 ### Include an id string (For safe flashing)
67 mainboardinit arch/i386/lib/id.inc
68 ldscript /arch/i386/lib/id.lds
71 #### This is the early phase of linuxBIOS startup
72 #### Things are delicate and we test to see if we should
73 #### failover to another image.
75 #option MAX_REBOOT_CNT=2
77 ldscript /arch/i386/lib/failover.lds
83 mainboardinit cpu/k8/earlymtrr.inc
85 ### Only the bootstrap cpu makes it here.
86 ### Failover if we need to
90 mainboardinit ./failover.inc
96 ### Setup the serial port
98 #mainboardinit superiowinbond/w83627hf/setup_serial.inc
99 mainboardinit pc80/serial.inc
100 mainboardinit arch/i386/lib/console.inc
103 #### O.k. We aren't just an intermediary anymore!
107 ### When debugging disable the watchdog timer
109 ##option MAXIMUM_CONSOLE_LOGLEVEL=7
110 #default MAXIMUM_CONSOLE_LOGLEVEL=7
112 #if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end
117 #makerule ./failover.E dep "$(MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failever.E"
118 #makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc"
119 #mainboardinit .failover.inc
121 makerule ./failover.E
122 depends "$(MAINBOARD)/failover.c"
123 action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
126 makerule ./failover.inc
127 depends "./romcc ./failover.E"
128 action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"end
131 depends "$(MAINBOARD)/auto.c"
132 action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
135 depends "./romcc ./auto.E"
136 action "./romcc -O -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E"
137 # action "./romcc -mcpu=k8 -O ./auto.E > auto.inc"
139 mainboardinit cpu/k8/enable_mmx_sse.inc
140 mainboardinit ./auto.inc
141 mainboardinit cpu/k8/disable_mmx_sse.inc
144 ### Include the secondary Configuration files
146 northbridge amd/amdk8 "mc0"
153 southbridge amd/amd8111 "amd8111" link 0
168 #northbridge amd/amdk8
170 #southbridge amd/amd8111 "amd8111"
172 #mainboardinit archi386/smp/secondary.inc
174 # register "com1" = "{1}"
175 # register "lpt" = "{1}"
178 ##dir /src/superio/winbond/w83627hf
182 register "up" = "{.chip = &amd8111, .ht_width=8, .ht_speed=200}"