1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <device/pci.h>
7 static void *smp_write_config_table(void *v)
9 static const char sig[4] = "PCMP";
10 static const char oem[8] = "COREBOOT";
11 static const char productid[12] = "S2735 ";
12 struct mp_config_table *mc;
14 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
15 memset(mc, 0, sizeof(*mc));
17 memcpy(mc->mpc_signature, sig, sizeof(sig));
18 mc->mpc_length = sizeof(*mc); /* initially just the header */
20 mc->mpc_checksum = 0; /* not yet computed */
21 memcpy(mc->mpc_oem, oem, sizeof(oem));
22 memcpy(mc->mpc_productid, productid, sizeof(productid));
25 mc->mpc_entry_count = 0; /* No entries yet... */
26 mc->mpc_lapic = LAPIC_ADDR;
31 smp_write_processors(mc);
35 smp_write_bus(mc, 0, "PCI ");
36 smp_write_bus(mc, 1, "PCI ");
37 smp_write_bus(mc, 2, "PCI ");
38 smp_write_bus(mc, 3, "PCI ");
39 smp_write_bus(mc, 4, "PCI ");
40 smp_write_bus(mc, 5, "ISA ");
41 /*I/O APICs: APIC ID Version State Address*/
42 smp_write_ioapic(mc, 8, 0x20, 0xfec00000);
46 dev = dev_find_slot(1, PCI_DEVFN(0x1e,0));
48 res = find_resource(dev, PCI_BASE_ADDRESS_0);
50 smp_write_ioapic(mc, 0x09, 0x20, res->base);
53 dev = dev_find_slot(1, PCI_DEVFN(0x1c,0));
55 res = find_resource(dev, PCI_BASE_ADDRESS_0);
57 smp_write_ioapic(mc, 0x0a, 0x20, res->base);
61 mptable_add_isa_interrupts(mc, 0x5, 0x8, 0);
63 /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#
66 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7c, 0x8, 0x12);
67 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x8, 0x11);
68 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x8, 0x10);
69 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x8, 0x13);
70 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x8, 0x17);
73 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x8, 0x8, 0x12);
75 //onboard intel 82551 10/100
76 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x4, 0x8, 0x11);
78 // onboard Intel 82547 1000
79 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x4, 0xa, 0x0);
80 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x5, 0xa, 0x1);
83 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x3<<2)|0, 0x8, 0x12);
84 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x3<<2)|1, 0x8, 0x13);
85 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x3<<2)|2, 0x8, 0x10);
86 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x3<<2)|3, 0x8, 0x11);
88 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x4<<2)|0, 0x8, 0x13);
89 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x4<<2)|1, 0x8, 0x10);
90 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x4<<2)|2, 0x8, 0x11);
91 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x4<<2)|3, 0x8, 0x12);
93 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x3<<2)|0, 0x9, 0x0);
94 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x3<<2)|1, 0x9, 0x1);
95 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x3<<2)|2, 0x9, 0x2);
96 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x3<<2)|3, 0x9, 0x3);
98 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x6<<2)|0, 0x9, 0x4);
99 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x6<<2)|1, 0x9, 0x5);
100 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x6<<2)|2, 0x9, 0x6);
101 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x6<<2)|3, 0x9, 0x7);
103 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
104 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x0, 0x0, MP_APIC_ALL, 0x0);
105 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x0, 0x0, MP_APIC_ALL, 0x1);
107 MP Config Extended Table Entries:
111 bus ID: 0 address type: I/O address
113 address range: 0x6000
116 bus ID: 0 address type: I/O address
121 bus ID: 0 address type: memory address
122 address base: 0xa0000
123 address range: 0x20000
126 bus ID: 0 address type: memory address
127 address base: 0xfc700000
128 address range: 0x2500000
131 bus ID: 0 address type: prefetch address
132 address base: 0xff600000
133 address range: 0x500000
136 bus ID: 5 bus info: 0x01 parent bus ID: 0--
137 Compatibility Bus Address
138 bus ID: 0 address modifier: add
139 predefined range: 0x00000000--
140 Compatibility Bus Address
141 bus ID: 0 address modifier: add
142 predefined range: 0x00000001 // There is no extension information...
144 /* Compute the checksums */
145 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
146 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
147 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
148 mc, smp_next_mpe_entry(mc));
149 return smp_next_mpe_entry(mc);
152 unsigned long write_smp_table(unsigned long addr)
155 v = smp_write_floating_table(addr);
156 return (unsigned long)smp_write_config_table(v);