src/mainboard/tyan/s2735/cache_as_ram_auto.c

   1 #define ASSEMBLY 1
   2 #define __ROMCC__
   3
   4 #include <stdint.h>
   5 #include <string.h>
   6 #include <device/pci_def.h>
   7 #include <arch/io.h>
   8 #include <device/pnp_def.h>
   9 #include <arch/romcc_io.h>
  10 #include <cpu/x86/lapic.h>
  11 #include "option_table.h"
  12 #include "pc80/mc146818rtc_early.c"
  13 #include "pc80/serial.c"
  14 #include "arch/i386/lib/console.c"
  15 #include "ram/ramtest.c"
  16
  17 #if 0
  18 static void post_code(uint8_t value) {
  19 #if 1
  20         int i;
  21         for(i=0;i<0x80000;i++) {
  22                 outb(value, 0x80);
  23         }
  24 #endif
  25 }
  26 #endif
  27
  28 #include "southbridge/intel/i82801er/i82801er_early_smbus.c"
  29 #include "northbridge/intel/e7501/raminit.h"
  30
  31 #include "cpu/x86/lapic/boot_cpu.c"
  32 #include "northbridge/intel/e7501/debug.c"
  33 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  34
  35 #include "cpu/x86/mtrr/earlymtrr.c"
  36 #include "cpu/x86/bist.h"
  37
  38 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  39
  40 static void hard_reset(void)
  41 {
  42         /* full reset */
  43         outb(0x0a, 0x0cf9);
  44         outb(0x0e, 0x0cf9);
  45 }
  46
  47 static void soft_reset(void)
  48 {
  49 #if 1
  50         /* link reset */
  51         outb(0x02, 0x0cf9);
  52         outb(0x06, 0x0cf9);
  53 #endif
  54 }
  55
  56 static void memreset_setup(void)
  57 {
  58 }
  59
  60 static void memreset(int controllers, const struct mem_controller *ctrl)
  61 {
  62 }
  63
  64 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  65 {
  66         /* nothing to do */
  67 }
  68
  69 static inline int spd_read_byte(unsigned device, unsigned address)
  70 {
  71         return smbus_read_byte(device, address);
  72 }
  73
  74
  75 #include "northbridge/intel/e7501/raminit.c"
  76 #include "northbridge/intel/e7501/reset_test.c"
  77 #include "sdram/generic_sdram.c"
  78
  79
  80 #include "cpu/x86/car/copy_and_run.c"
  81
  82 #if USE_FALLBACK_IMAGE == 1
  83
  84 #include "southbridge/intel/i82801er/cmos_failover.c"
  85
  86 void real_main(unsigned long bist);
  87
  88 void amd64_main(unsigned long bist)
  89 {
  90         /* Is this a deliberate reset by the bios */
  91 //        post_code(0x22);
  92         if (bios_reset_detected() && last_boot_normal()) {
  93                 goto normal_image;
  94         }
  95         /* This is the primary cpu how should I boot? */
  96         else {
  97                 check_cmos_failed();
  98                 if (do_normal_boot()) {
  99                         goto normal_image;
 100                 }
 101                 else {
 102                         goto fallback_image;
 103                 }
 104         }
 105  normal_image:
 106 //        post_code(0x23);
 107         __asm__ volatile ("jmp __normal_image"
 108                 : /* outputs */
 109                 : "a" (bist) /* inputs */
 110                 );
 111  cpu_reset:
 112 //        post_code(0x24);
 113 #if 0
 114         //CPU reset will reset memtroller ???
 115         asm volatile ("jmp __cpu_reset"
 116                 : /* outputs */
 117                 : "a"(bist) /* inputs */
 118                 );
 119 #endif
 120
 121  fallback_image:
 122 //        post_code(0x25);
 123         real_main(bist);
 124 }
 125 void real_main(unsigned long bist)
 126 #else
 127 void amd64_main(unsigned long bist)
 128 #endif
 129 {
 130         static const struct mem_controller memctrl[] = {
 131                 {
 132                         .d0 = PCI_DEV(0, 0, 0),
 133                         .d0f1 = PCI_DEV(0, 0, 1),
 134                         .channel0 = { (0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, 0 },
 135                         .channel1 = { (0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, 0 },
 136                 },
 137         };
 138
 139         unsigned cpu_reset = 0;
 140
 141        if (bist == 0)
 142         {
 143 //              early_mtrr_init();
 144                 enable_lapic();
 145
 146         }
 147
 148 //      post_code(0x32);
 149
 150         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 151         uart_init();
 152         console_init();
 153
 154         /* Halt if there was a built in self test failure */
 155         report_bist_failure(bist);
 156
 157 //        setup_s2735_resource_map();
 158
 159         if(bios_reset_detected()) {
 160                 cpu_reset = 1;
 161                 goto cpu_reset_x;
 162         }
 163
 164         enable_smbus();
 165 #if 0
 166         dump_spd_registers(&memctrl[0]);
 167 #endif
 168 #if 0
 169         dump_smbus_registers();
 170 #endif
 171
 172         memreset_setup();
 173         sdram_initialize(1, memctrl);
 174
 175 #if 0
 176         dump_pci_devices();
 177 #endif
 178
 179 #if 1
 180         dump_pci_device(PCI_DEV(0, 0, 0));
 181 #endif
 182
 183
 184 #if 1
 185         {
 186                 /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
 187                 unsigned v_esp;
 188                 __asm__ volatile (
 189                         "movl   %%esp, %0\n\t"
 190                         : "=a" (v_esp)
 191                 );
 192 #if CONFIG_USE_INIT
 193                 printk_debug("v_esp=%08x\r\n", v_esp);
 194 #else
 195                 print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n");
 196 #endif
 197         }
 198
 199 #endif
 200 #if 1
 201
 202 cpu_reset_x:
 203
 204 #if CONFIG_USE_INIT
 205         printk_debug("cpu_reset = %08x\r\n",cpu_reset);
 206 #else
 207         print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n");
 208 #endif
 209
 210         if(cpu_reset == 0) {
 211                 print_debug("Clearing initial memory region: ");
 212         }
 213         print_debug("No cache as ram now - ");
 214
 215         /* store cpu_reset to ebx */
 216         __asm__ volatile (
 217                 "movl %0, %%ebx\n\t"
 218                 ::"a" (cpu_reset)
 219         );
 220
 221         if(cpu_reset==0) {
 222 #define CLEAR_FIRST_1M_RAM 1
 223 #include "cpu/x86/car/cache_as_ram_post.c"
 224         }
 225         else {
 226 #undef CLEAR_FIRST_1M_RAM
 227 #include "cpu/x86/car/cache_as_ram_post.c"
 228         }
 229
 230         __asm__ volatile (
 231                 /* set new esp */ /* before _RAMBASE */
 232                 "subl   %0, %%ebp\n\t"
 233                 "subl   %0, %%esp\n\t"
 234                 ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE )
 235         );
 236
 237         {
 238                 unsigned new_cpu_reset;
 239
 240                 /* get back cpu_reset from ebx */
 241                 __asm__ volatile (
 242                         "movl %%ebx, %0\n\t"
 243                         :"=a" (new_cpu_reset)
 244                 );
 245
 246                 /* We can not go back any more, we lost old stack data in cache as ram*/
 247                 if(new_cpu_reset==0) {
 248                         print_debug("Use Ram as Stack now - done\r\n");
 249                 } else
 250                 {
 251                         print_debug("Use Ram as Stack now - \r\n");
 252                 }
 253 #if CONFIG_USE_INIT
 254                 printk_debug("new_cpu_reset = %08x\r\n", new_cpu_reset);
 255 #else
 256                 print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n");
 257 #endif
 258
 259 #ifdef CONFIG_DEACTIVATE_CAR
 260                 print_debug("Deactivating CAR");
 261 #include CONFIG_DEACTIVATE_CAR_FILE
 262                 print_debug(" - Done.\r\n");
 263 #endif
 264                 /*copy and execute coreboot_ram */
 265                 copy_and_run(new_cpu_reset);
 266                 /* We will not return */
 267         }
 268 #endif
 269
 270
 271         print_debug("should not be here -\r\n");
 272
 273 }