src/mainboard/tyan/s2735/auto.c

   1 #define ASSEMBLY 1
   2
   3 #include <stdint.h>
   4 #include <device/pci_def.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <cpu/x86/lapic.h>
   9 #include <arch/cpu.h>
  10 #include "option_table.h"
  11 #include "pc80/mc146818rtc_early.c"
  12 #include "pc80/serial.c"
  13 #include "arch/i386/lib/console.c"
  14 #include "ram/ramtest.c"
  15 #include "southbridge/intel/i82801er/i82801er_early_smbus.c"
  16 #include "northbridge/intel/e7501/raminit.h"
  17 #if 0
  18 #include "cpu/intel/model_f2x/apic_timer.c"
  19 #include "lib/delay.c"
  20 #endif
  21 #include "cpu/x86/lapic/boot_cpu.c"
  22 #include "northbridge/intel/e7501/debug.c"
  23 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  24 #include "cpu/x86/mtrr/earlymtrr.c"
  25 #include "cpu/x86/bist.h"
  26
  27 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  28
  29 static void hard_reset(void)
  30 {
  31         outb(0x0e, 0x0cf9);
  32 }
  33
  34 static void memreset_setup(void)
  35 {
  36 }
  37
  38 static void memreset(int controllers, const struct mem_controller *ctrl)
  39 {
  40 }
  41
  42
  43
  44 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  45 {
  46         /* nothing to do */
  47 }
  48
  49 static inline int spd_read_byte(unsigned device, unsigned address)
  50 {
  51         return smbus_read_byte(device, address);
  52 }
  53
  54 #include "northbridge/intel/e7501/raminit.c"
  55 #include "northbridge/intel/e7501/reset_test.c"
  56 #include "sdram/generic_sdram.c"
  57
  58 static void main(unsigned long bist)
  59 {
  60         static const struct mem_controller memctrl[] = {
  61                 {
  62                         .d0 = PCI_DEV(0, 0, 0),
  63                         .d0f1 = PCI_DEV(0, 0, 1),
  64                         .channel0 = { (0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, 0 },
  65                         .channel1 = { (0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, 0 },
  66                 },
  67         };
  68
  69         if (bist == 0) {
  70                 /* Skip this if there was a built in self test failure */
  71                 early_mtrr_init();
  72                 enable_lapic();
  73                 init_timer();
  74
  75         }
  76
  77         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
  78         uart_init();
  79         console_init();
  80
  81         /* Halt if there was a built in self test failure */
  82         report_bist_failure(bist);
  83
  84 //        setup_default_resource_map();
  85 #if 0
  86         print_pci_devices();
  87 #endif
  88         if(!bios_reset_detected()) {
  89                 enable_smbus();
  90 #if 0
  91 //              dump_spd_registers(&memctrl[0]);
  92                 dump_smbus_registers();
  93 #endif
  94
  95                 memreset_setup();
  96                 sdram_initialize(sizeof(memctrl)/sizeof(memctrl[0]), memctrl);
  97         }
  98 #if 0
  99         else {
 100                         /* clear memory 1meg */
 101         __asm__ volatile(
 102                 "1: \n\t"
 103                 "movl %0, %%fs:(%1)\n\t"
 104                 "addl $4,%1\n\t"
 105                 "subl $4,%2\n\t"
 106                 "jnz 1b\n\t"
 107                 :
 108                 : "a" (0), "D" (0), "c" (1024*1024)
 109                 );
 110
 111         }
 112 #endif
 113
 114 #if 0
 115         dump_pci_devices();
 116 #endif
 117 #if 0
 118         dump_pci_device(PCI_DEV(0, 0, 0));
 119 #endif
 120
 121 #if 0
 122         msr_t msr;
 123         msr = rdmsr(TOP_MEM2);
 124         print_debug("TOP_MEM2: ");
 125         print_debug_hex32(msr.hi);
 126         print_debug_hex32(msr.lo);
 127         print_debug("\r\n");
 128 #endif
 129 /*
 130 #if  0
 131         ram_check(0x00000000, msr.lo+(msr.hi<<32));
 132 #else
 133 #if 0
 134         // Check 16MB of memory @ 0
 135         ram_check(0x00000000, 0x01000000);
 136 #else
 137         // Check 16MB of memory @ 2GB
 138         ram_check(0x80000000, 0x81000000);
 139 #endif
 140 #endif
 141 */
 142 }