3 uses USE_FALLBACK_IMAGE
4 uses HAVE_FALLBACK_BOOT
8 uses HARD_RESET_FUNCTION
10 uses HAVE_OPTION_TABLE
12 uses CONFIG_LOGICAL_CPUS
20 uses ROM_SECTION_OFFSET
21 uses CONFIG_ROM_STREAM
22 uses CONFIG_ROM_STREAM_START
30 uses LB_CKS_RANGE_START
33 uses MAINBOARD_PART_NUMBER
36 uses LINUXBIOS_EXTRA_VERSION
41 uses DEFAULT_CONSOLE_LOGLEVEL
42 uses MAXIMUM_CONSOLE_LOGLEVEL
43 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
44 uses CONFIG_CONSOLE_SERIAL8250
45 uses CONFIG_UDELAY_TSC
46 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
60 ## ROM_SIZE is the size of boot ROM that this board will use.
62 #default ROM_SIZE=524288
65 default ROM_SIZE=1048576
68 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
70 default FALLBACK_SIZE=131072
73 ## Build code for the fallback boot
75 default HAVE_FALLBACK_BOOT=1
78 ## Build code to reset the motherboard from linuxBIOS
80 default HAVE_HARD_RESET=1
83 ## Funky hard reset implementation
85 #default HARD_RESET_BUS=3
86 #default HARD_RESET_DEVICE=4
87 #default HARD_RESET_FUNCTION=0
89 ## Delay timer options
91 default CONFIG_UDELAY_TSC=1
92 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
95 ## Build code to export a programmable irq routing table
97 default HAVE_PIRQ_TABLE=1
98 default IRQ_SLOT_COUNT=15
101 ## Build code to export an x86 MP table
102 ## Useful for specifying IRQ routing values
104 default HAVE_MP_TABLE=1
107 ## Build code to export a CMOS option table
109 default HAVE_OPTION_TABLE=1
112 ## Move the default LinuxBIOS cmos range off of AMD RTC registers
114 default LB_CKS_RANGE_START=49
115 default LB_CKS_RANGE_END=122
116 default LB_CKS_LOC=123
119 ## Build code for SMP support
120 ## Only worry about 2 micro processors
123 default CONFIG_MAX_CPUS=4
124 default CONFIG_LOGICAL_CPUS=1
127 ## Build code to setup a generic IOAPIC
129 default CONFIG_IOAPIC=1
132 ## Clean up the motherboard id strings
134 default MAINBOARD_PART_NUMBER="Tyan"
135 default MAINBOARD_VENDOR="s2735"
138 ### LinuxBIOS layout values
141 ## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
142 default ROM_IMAGE_SIZE = 65536
145 ## Use a small 8K stack
147 default STACK_SIZE=0x2000
150 ## Use a small 16K heap
152 default HEAP_SIZE=0x4000
155 ## Only use the option table in a normal image
157 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
160 ## LinuxBIOS C code runs at this location in RAM
162 default _RAMBASE=0x00004000
165 ## Load the payload from the ROM
167 default CONFIG_ROM_STREAM = 1
170 ### Defaults of options that you may want to override in the target config file
174 ## The default compiler
176 default CC="$(CROSS_COMPILE)gcc -m32"
180 ## Disable the gdb stub by default
182 default CONFIG_GDB_STUB=0
185 ## The Serial Console
188 # To Enable the Serial Console
189 default CONFIG_CONSOLE_SERIAL8250=1
191 ## Select the serial console baud rate
192 default TTYS0_BAUD=115200
193 #default TTYS0_BAUD=57600
194 #default TTYS0_BAUD=38400
195 #default TTYS0_BAUD=19200
196 #default TTYS0_BAUD=9600
197 #default TTYS0_BAUD=4800
198 #default TTYS0_BAUD=2400
199 #default TTYS0_BAUD=1200
201 # Select the serial console base port
202 default TTYS0_BASE=0x3f8
204 # Select the serial protocol
205 # This defaults to 8 data bits, 1 stop bit, and no parity
206 default TTYS0_LCS=0x3
209 ### Select the linuxBIOS loglevel
211 ## EMERG 1 system is unusable
212 ## ALERT 2 action must be taken immediately
213 ## CRIT 3 critical conditions
214 ## ERR 4 error conditions
215 ## WARNING 5 warning conditions
216 ## NOTICE 6 normal but significant condition
217 ## INFO 7 informational
218 ## DEBUG 8 debug-level messages
219 ## SPEW 9 Way too many details
221 ## Request this level of debugging output
222 default DEFAULT_CONSOLE_LOGLEVEL=8
223 ## At a maximum only compile in this level of debugging
224 default MAXIMUM_CONSOLE_LOGLEVEL=8
227 ## Select power on after power fail setting
228 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"