2 ## Compute the location and size of where this firmware image
3 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
6 default ROM_SECTION_SIZE = FALLBACK_SIZE
7 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
9 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
10 default ROM_SECTION_OFFSET = 0
14 ## Compute the start location and size size of
15 ## The linuxBIOS bootloader.
17 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
18 default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
21 ## Compute where this copy of linuxBIOS will start in the boot rom
23 default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
26 ## Compute a range of ROM that can cached to speed up linuxBIOS,
29 ## XIP_ROM_SIZE must be a power of 2.
30 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
32 default XIP_ROM_SIZE=65536
33 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
38 ## Build the objects we have code for in this directory.
42 if HAVE_MP_TABLE object mptable.o end
43 if HAVE_PIRQ_TABLE object irq_tables.o end
50 depends "$(MAINBOARD)/failover.c"
51 action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
54 makerule ./failover.inc
55 depends "./failover.E ./romcc"
56 action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
60 depends "$(MAINBOARD)/auto.c option_table.h "
61 action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
64 depends "./auto.E ./romcc"
65 action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
69 ## Build our 16 bit and 32 bit linuxBIOS entry code
71 mainboardinit cpu/x86/16bit/entry16.inc
72 mainboardinit cpu/x86/32bit/entry32.inc
73 ldscript /cpu/x86/16bit/entry16.lds
74 ldscript /cpu/x86/32bit/entry32.lds
77 ## Build our reset vector (This is where linuxBIOS is entered)
80 mainboardinit cpu/x86/16bit/reset16.inc
81 ldscript /cpu/x86/16bit/reset16.lds
83 mainboardinit cpu/x86/32bit/reset32.inc
84 ldscript /cpu/x86/32bit/reset32.lds
87 ### Should this be in the northbridge code?
88 mainboardinit arch/i386/lib/cpu_reset.inc
91 ## Include an id string (For safe flashing)
93 mainboardinit arch/i386/lib/id.inc
94 ldscript /arch/i386/lib/id.lds
97 ### This is the early phase of linuxBIOS startup
98 ### Things are delicate and we test to see if we should
99 ### failover to another image.
101 if USE_FALLBACK_IMAGE
102 ldscript /arch/i386/lib/failover.lds
103 mainboardinit ./failover.inc
107 ### O.k. We aren't just an intermediary anymore!
113 mainboardinit cpu/x86/fpu/enable_fpu.inc
114 mainboardinit cpu/x86/mmx/enable_mmx.inc
115 mainboardinit cpu/x86/sse/enable_sse.inc
116 mainboardinit ./auto.inc
117 mainboardinit cpu/x86/sse/disable_sse.inc
118 mainboardinit cpu/x86/mmx/disable_mmx.inc
121 ## Include the secondary Configuration files
126 # sample config for tyan/s2735
127 chip northbridge/intel/e7501
128 device pci_domain 0 on
129 device pci 0.0 on end
130 device pci 0.1 on end
132 chip southbridge/intel/i82870
133 device pci 1c.0 on end
134 device pci 1d.0 on end
135 device pci 1e.0 on end
136 device pci 1f.0 on end
139 device pci 6.0 on end
140 chip southbridge/intel/i82801er
141 device pci 1d.0 on end
142 device pci 1d.1 on end
143 device pci 1d.2 on end
144 device pci 1d.3 on end
145 device pci 1d.7 on end
146 device pci 1e.0 on end
149 chip superio/winbond/w83627hf
150 device pnp 2e.0 on # Floppy
155 device pnp 2e.1 off # Parallel Port
159 device pnp 2e.2 on # Com1
163 device pnp 2e.3 off # Com2
167 device pnp 2e.5 on # Keyboard
173 device pnp 2e.6 off end # CIR
174 device pnp 2e.7 off end # GAME_MIDI_GIPO1
175 device pnp 2e.8 off end # GPIO2
176 device pnp 2e.9 off end # GPIO3
177 device pnp 2e.a off end # ACPI
178 device pnp 2e.b on # HW Monitor
183 device pci 1f.1 off end
184 device pci 1f.2 on end
185 device pci 1f.3 on end
186 device pci 1f.5 off end
187 device pci 1f.6 off end
191 device apic_cluster 0 on
192 chip cpu/intel/socket_mPGA604_533Mhz
195 chip cpu/intel/socket_mPGA604_533Mhz