1 include /config/nofailovercalculation.lb
2 default CONFIG_ROM_PAYLOAD = 1
7 ## Build the objects we have code for in this directory.
11 if HAVE_MP_TABLE object mptable.o end
12 if HAVE_PIRQ_TABLE object irq_tables.o end
17 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
18 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
24 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
25 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
26 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
27 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
33 ## Build our 16 bit and 32 bit coreboot entry code
35 mainboardinit cpu/x86/16bit/entry16.inc
36 mainboardinit cpu/x86/32bit/entry32.inc
37 ldscript /cpu/x86/16bit/entry16.lds
39 ldscript /cpu/x86/32bit/entry32.lds
43 ldscript /cpu/x86/car/cache_as_ram.lds
48 ## Build our reset vector (This is where coreboot is entered)
51 mainboardinit cpu/x86/16bit/reset16.inc
52 ldscript /cpu/x86/16bit/reset16.lds
54 mainboardinit cpu/x86/32bit/reset32.inc
55 ldscript /cpu/x86/32bit/reset32.lds
59 ## Include an id string (For safe flashing)
61 mainboardinit arch/i386/lib/id.inc
62 ldscript /arch/i386/lib/id.lds
67 mainboardinit cpu/x86/car/cache_as_ram.inc
70 ### This is the early phase of coreboot startup
71 ### Things are delicate and we test to see if we should
72 ### failover to another image.
75 ldscript /arch/i386/lib/failover.lds
84 mainboardinit ./auto.inc
88 ## Include the secondary Configuration files
92 # sample config for tyan/s2735
93 chip northbridge/intel/e7501
94 device pci_domain 0 on
98 chip southbridge/intel/i82870
99 device pci 1c.0 on end
101 chip drivers/pci/onboard
102 device pci 1.0 on end # intel lan
103 device pci 1.1 on end
106 device pci 1e.0 on end
107 device pci 1f.0 on end
110 device pci 6.0 on end
111 chip southbridge/intel/i82801er
112 device pci 1d.0 on end
113 device pci 1d.1 on end
114 device pci 1d.2 on end
115 device pci 1d.3 on end
116 device pci 1d.7 on end
118 chip drivers/pci/onboard
119 device pci 1.0 on end # intel lan 10/100
121 chip drivers/pci/onboard
122 device pci 2.0 on end # ati
126 chip superio/winbond/w83627hf
127 device pnp 2e.0 on # Floppy
132 device pnp 2e.1 off # Parallel Port
136 device pnp 2e.2 on # Com1
140 device pnp 2e.3 on # Com2
144 device pnp 2e.5 on # Keyboard
150 device pnp 2e.6 off # CIR
153 device pnp 2e.7 off # GAME_MIDI_GIPO1
158 device pnp 2e.8 off end # GPIO2
159 device pnp 2e.9 off end # GPIO3
160 device pnp 2e.a off end # ACPI
161 device pnp 2e.b on # HW Monitor
167 device pci 1f.1 off end
168 device pci 1f.2 on end
169 device pci 1f.3 on end
170 device pci 1f.5 off end
171 device pci 1f.6 off end
174 device apic_cluster 0 on
175 chip cpu/intel/socket_mPGA604_533Mhz
178 chip cpu/intel/socket_mPGA604_533Mhz