Thanks to Myles' patch adding support for include statements,
[coreboot.git] / src / mainboard / tyan / s2735 / Config.lb
1 include /config/nofailovercalculation.lb
2 default CONFIG_ROM_PAYLOAD = 1
3
4 arch i386 end 
5
6 ##
7 ## Build the objects we have code for in this directory.
8 ##
9
10 driver mainboard.o
11 if HAVE_MP_TABLE object mptable.o end
12 if HAVE_PIRQ_TABLE object irq_tables.o end
13 object reset.o
14 if CONFIG_USE_INIT
15
16 makerule ./auto.o
17         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
18         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
19 end
20
21 else
22
23 makerule ./auto.inc
24         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
25         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
26         action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
27         action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
28 end
29
30 end
31
32 ##
33 ## Build our 16 bit and 32 bit coreboot entry code
34 ##
35 mainboardinit cpu/x86/16bit/entry16.inc
36 mainboardinit cpu/x86/32bit/entry32.inc
37 ldscript /cpu/x86/16bit/entry16.lds
38         if CONFIG_USE_INIT
39                 ldscript /cpu/x86/32bit/entry32.lds
40         end
41
42         if CONFIG_USE_INIT
43                 ldscript      /cpu/x86/car/cache_as_ram.lds
44         end
45
46
47 ##
48 ## Build our reset vector (This is where coreboot is entered)
49 ##
50 if USE_FALLBACK_IMAGE 
51         mainboardinit cpu/x86/16bit/reset16.inc 
52         ldscript /cpu/x86/16bit/reset16.lds 
53 else
54         mainboardinit cpu/x86/32bit/reset32.inc 
55         ldscript /cpu/x86/32bit/reset32.lds 
56 end
57
58 ##
59 ## Include an id string (For safe flashing)
60 ##
61 mainboardinit arch/i386/lib/id.inc
62 ldscript /arch/i386/lib/id.lds
63
64 ##
65 ## Setup Cache-As-Ram
66 ##
67 mainboardinit cpu/x86/car/cache_as_ram.inc
68
69 ###
70 ### This is the early phase of coreboot startup 
71 ### Things are delicate and we test to see if we should
72 ### failover to another image.
73 ###
74 if USE_FALLBACK_IMAGE
75        ldscript /arch/i386/lib/failover.lds
76 end
77
78 ##
79 ## Setup RAM
80 ##
81 if CONFIG_USE_INIT
82 initobject auto.o
83 else
84 mainboardinit ./auto.inc
85 end
86
87 ##
88 ## Include the secondary Configuration files 
89 ##
90 config chip.h
91
92 # sample config for tyan/s2735
93 chip northbridge/intel/e7501
94         device pci_domain 0 on
95                 device pci 0.0 on end
96                 device pci 0.1 on end
97                 device pci 2.0 on
98                         chip southbridge/intel/i82870
99                                 device pci 1c.0 on end
100                                 device pci 1d.0 on 
101                                         chip drivers/pci/onboard
102                                                 device pci 1.0 on end # intel lan
103                                                 device pci 1.1 on end
104                                         end
105                                 end
106                                 device pci 1e.0 on end
107                                 device pci 1f.0 on end
108                         end
109                 end
110                 device pci 6.0 on end
111                 chip southbridge/intel/i82801er
112                         device pci 1d.0 on end
113                         device pci 1d.1 on end
114                         device pci 1d.2 on end
115                         device pci 1d.3 on end
116                         device pci 1d.7 on end
117                         device pci 1e.0 on 
118                                 chip drivers/pci/onboard
119                                         device pci 1.0 on end # intel lan 10/100
120                                 end
121                                 chip drivers/pci/onboard
122                                         device pci 2.0 on end # ati 
123                                 end
124                         end
125                         device pci 1f.0 on
126                                 chip superio/winbond/w83627hf
127                                         device pnp 2e.0 on #  Floppy
128                                                 io 0x60 = 0x3f0
129                                                 irq 0x70 = 6
130                                                 drq 0x74 = 2
131                                         end
132                                         device pnp 2e.1 off #  Parallel Port
133                                                 io 0x60 = 0x378
134                                                 irq 0x70 = 7
135                                         end
136                                         device pnp 2e.2 on #  Com1
137                                                 io 0x60 = 0x3f8
138                                                 irq 0x70 = 4
139                                         end
140                                         device pnp 2e.3 on #  Com2
141                                                 io 0x60 = 0x2f8
142                                                 irq 0x70 = 3
143                                         end
144                                         device pnp 2e.5 on #  Keyboard
145                                                 io 0x60 = 0x60
146                                                 io 0x62 = 0x64
147                                                 irq 0x70 = 1
148                                                 irq 0x72 = 12
149                                         end
150                                         device pnp 2e.6 off #  CIR
151                                                 io 0x60 = 0x100
152                                         end
153                                         device pnp 2e.7 off #  GAME_MIDI_GIPO1
154                                                 io 0x60 = 0x220
155                                                 io 0x62 = 0x300
156                                                 irq 0x70 = 9
157                                         end                               
158                                         device pnp 2e.8 off end #  GPIO2
159                                         device pnp 2e.9 off end #  GPIO3
160                                         device pnp 2e.a off end #  ACPI
161                                         device pnp 2e.b on #  HW Monitor
162                                                 io 0x60 = 0x290
163                                                 irq 0x70 = 5
164                                         end
165                                 end
166                         end
167                         device pci 1f.1 off end
168                         device pci 1f.2 on end
169                         device pci 1f.3 on end
170                         device pci 1f.5 off end
171                         device pci 1f.6 off end
172                 end # SB
173         end # PCI_DOMAIN
174         device apic_cluster 0 on
175                 chip cpu/intel/socket_mPGA604_533Mhz
176                         device apic 0 on end
177                 end
178                 chip cpu/intel/socket_mPGA604_533Mhz
179                         device apic 6 on end
180                 end
181         end
182 end
183