2 ## Compute the location and size of where this firmware image
3 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
6 default ROM_SECTION_SIZE = FALLBACK_SIZE
7 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
9 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
10 default ROM_SECTION_OFFSET = 0
14 ## Compute the start location and size size of
15 ## The linuxBIOS bootloader.
17 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
18 default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
21 ## Compute where this copy of linuxBIOS will start in the boot rom
23 default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
26 ## Compute a range of ROM that can cached to speed up linuxBIOS,
29 ## XIP_ROM_SIZE must be a power of 2.
30 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
32 default XIP_ROM_SIZE=65536
33 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
38 ## Build the objects we have code for in this directory.
42 if HAVE_MP_TABLE object mptable.o end
43 if HAVE_PIRQ_TABLE object irq_tables.o end
51 depends "$(MAINBOARD)/failover.c ./romcc"
52 action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
55 makerule ./failover.inc
56 depends "$(MAINBOARD)/failover.c ./romcc"
57 action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
61 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
62 action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
65 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
66 action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
70 ## Build our 16 bit and 32 bit linuxBIOS entry code
72 mainboardinit cpu/x86/16bit/entry16.inc
73 mainboardinit cpu/x86/32bit/entry32.inc
74 ldscript /cpu/x86/16bit/entry16.lds
75 ldscript /cpu/x86/32bit/entry32.lds
78 ## Build our reset vector (This is where linuxBIOS is entered)
81 mainboardinit cpu/x86/16bit/reset16.inc
82 ldscript /cpu/x86/16bit/reset16.lds
84 mainboardinit cpu/x86/32bit/reset32.inc
85 ldscript /cpu/x86/32bit/reset32.lds
88 ### Should this be in the northbridge code?
89 mainboardinit arch/i386/lib/cpu_reset.inc
92 ## Include an id string (For safe flashing)
94 mainboardinit arch/i386/lib/id.inc
95 ldscript /arch/i386/lib/id.lds
98 ### This is the early phase of linuxBIOS startup
99 ### Things are delicate and we test to see if we should
100 ### failover to another image.
102 if USE_FALLBACK_IMAGE
103 ldscript /arch/i386/lib/failover.lds
104 mainboardinit ./failover.inc
108 ### O.k. We aren't just an intermediary anymore!
114 mainboardinit cpu/x86/fpu/enable_fpu.inc
115 mainboardinit cpu/x86/mmx/enable_mmx.inc
116 mainboardinit cpu/x86/sse/enable_sse.inc
117 mainboardinit ./auto.inc
118 mainboardinit cpu/x86/sse/disable_sse.inc
119 mainboardinit cpu/x86/mmx/disable_mmx.inc
122 ## Include the secondary Configuration files
130 # sample config for tyan/s2735
131 chip northbridge/intel/e7501
132 device pci_domain 0 on
133 device pci 0.0 on end
134 device pci 0.1 on end
136 chip southbridge/intel/i82870
137 device pci 1c.0 on end
138 device pci 1d.0 on end
139 device pci 1e.0 on end
140 device pci 1f.0 on end
143 device pci 6.0 on end
144 chip southbridge/intel/i82801er
145 device pci 1d.0 on end
146 device pci 1d.1 on end
147 device pci 1d.2 on end
148 device pci 1d.3 on end
149 device pci 1d.7 on end
150 device pci 1e.0 on end
153 chip superio/winbond/w83627hf
154 device pnp 2e.0 on # Floppy
159 device pnp 2e.1 off # Parallel Port
163 device pnp 2e.2 on # Com1
167 device pnp 2e.3 off # Com2
171 device pnp 2e.5 on # Keyboard
177 device pnp 2e.6 off end # CIR
178 device pnp 2e.7 off end # GAME_MIDI_GIPO1
179 device pnp 2e.8 off end # GPIO2
180 device pnp 2e.9 off end # GPIO3
181 device pnp 2e.a off end # ACPI
182 device pnp 2e.b on # HW Monitor
187 device pci 1f.1 off end
188 device pci 1f.2 on end
189 device pci 1f.3 on end
190 device pci 1f.5 off end
191 device pci 1f.6 off end
194 device apic_cluster 0 on
195 chip cpu/intel/socket_mPGA604_533Mhz
198 chip cpu/intel/socket_mPGA604_533Mhz