2 ## Compute the location and size of where this firmware image
3 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
6 default ROM_SECTION_SIZE = FALLBACK_SIZE
7 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
9 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
10 default ROM_SECTION_OFFSET = 0
14 ## Compute the start location and size size of
15 ## The linuxBIOS bootloader.
17 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
18 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
21 ## Compute where this copy of linuxBIOS will start in the boot rom
23 default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
26 ## Compute a range of ROM that can cached to speed up linuxBIOS,
29 ## XIP_ROM_SIZE must be a power of 2.
30 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
32 default XIP_ROM_SIZE=65536
33 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
36 ## Set all of the defaults for an x86 architecture
42 ## Build the objects we have code for in this directory.
47 #if HAVE_PIRQ_TABLE object irq_tables.o end
54 depends "$(MAINBOARD)/failover.c ./romcc"
55 action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
58 makerule ./failover.inc
59 depends "$(MAINBOARD)/failover.c ./romcc"
60 action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
64 depends "$(MAINBOARD)/auto.c ./romcc"
65 action "./romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
68 depends "$(MAINBOARD)/auto.c ./romcc"
69 action "./romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
73 ## Build our 16 bit and 32 bit linuxBIOS entry code
75 mainboardinit cpu/x86/16bit/entry16.inc
76 mainboardinit cpu/x86/32bit/entry32.inc
77 ldscript /cpu/x86/16bit/entry16.lds
78 ldscript /cpu/x86/32bit/entry32.lds
81 ## Build our reset vector (This is where linuxBIOS is entered)
84 mainboardinit cpu/x86/16bit/reset16.inc
85 ldscript /cpu/x86/16bit/reset16.lds
87 mainboardinit cpu/x86/32bit/reset32.inc
88 ldscript /cpu/x86/32bit/reset32.lds
91 ### Should this be in the northbridge code?
92 mainboardinit arch/i386/lib/cpu_reset.inc
95 ## Include an id string (For safe flashing)
97 mainboardinit arch/i386/lib/id.inc
98 ldscript /arch/i386/lib/id.lds
101 ### This is the early phase of linuxBIOS startup
102 ### Things are delicate and we test to see if we should
103 ### failover to another image.
105 if USE_FALLBACK_IMAGE
106 ldscript /arch/i386/lib/failover.lds
107 mainboardinit ./failover.inc
111 ### O.k. We aren't just an intermediary anymore!
117 mainboardinit cpu/x86/fpu/enable_fpu.inc
118 mainboardinit cpu/x86/mmx/enable_mmx.inc
119 mainboardinit ./auto.inc
120 mainboardinit cpu/x86/mmx/disable_mmx.inc
123 ## Include the secondary Configuration files
128 chip northbridge/intel/i440bx # Northbridge
129 device pci_domain 0 on
130 device pci 0.0 on end # Host bridge
131 device pci 1.0 on end # AGP bridge
132 chip southbridge/intel/i82371eb # Southbridge
133 device pci 7.0 on # ISA bridge
134 chip superio/nsc/pc87309 # Super I/O
135 device pnp 2e.5 on # PS/2 keyboard (+ mouse?)
141 device pnp 2e.b on # Com1
145 device pnp 2e.c on # Com2 / IR
149 device pnp 2e.d on # Parallel port
153 device pnp 2e.e on # Floppy
158 device pnp 2e.f on # PS/2 mouse
163 device pci 7.1 on end # IDE
164 device pci 7.2 on end # USB
165 device pci 7.3 on end # ACPI
166 register "ide0_enable" = "1"
167 register "ide1_enable" = "1"
170 chip cpu/intel/slot_2 # CPU