2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 default ROM_SECTION_SIZE = FALLBACK_SIZE
23 default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
25 default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
26 default ROM_SECTION_OFFSET = 0
28 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
29 default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
30 default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
31 default XIP_ROM_SIZE = 65536
32 default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
35 if HAVE_PIRQ_TABLE object irq_tables.o end
43 depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
44 action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
46 makerule ./failover.inc
47 depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
48 action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
51 # depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
52 depends "$(MAINBOARD)/auto.c ./romcc"
53 action "./romcc -E -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
56 # depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
57 depends "$(MAINBOARD)/auto.c ./romcc"
58 action "./romcc -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
60 mainboardinit cpu/x86/16bit/entry16.inc
61 mainboardinit cpu/x86/32bit/entry32.inc
62 ldscript /cpu/x86/16bit/entry16.lds
63 ldscript /cpu/x86/32bit/entry32.lds
65 mainboardinit cpu/x86/16bit/reset16.inc
66 ldscript /cpu/x86/16bit/reset16.lds
68 mainboardinit cpu/x86/32bit/reset32.inc
69 ldscript /cpu/x86/32bit/reset32.lds
71 mainboardinit arch/i386/lib/cpu_reset.inc
72 mainboardinit arch/i386/lib/id.inc
73 ldscript /arch/i386/lib/id.lds
75 ldscript /arch/i386/lib/failover.lds
76 mainboardinit ./failover.inc
78 mainboardinit cpu/x86/fpu/enable_fpu.inc
79 mainboardinit cpu/x86/mmx/enable_mmx.inc
80 mainboardinit ./auto.inc
81 mainboardinit cpu/x86/mmx/disable_mmx.inc
85 chip northbridge/intel/i82830 # Northbridge
86 device pci_domain 0 on # PCI domain
87 device pci 0.0 on end # Host bridge
88 chip drivers/pci/onboard # Onboard VGA
89 device pci 2.0 on end # VGA (Intel 82830 CGC)
90 register "rom_address" = "0xfff00000"
92 chip southbridge/intel/i82801xx # Southbridge
93 device pci 1d.0 on end # USB UHCI Controller #1
94 device pci 1d.1 on end # USB UHCI Controller #2
95 device pci 1d.2 on end # USB UHCI Controller #3
96 device pci 1d.7 on end # USB2 EHCI Controller
97 device pci 1e.0 on # PCI bridge
98 device pci 08.0 on end # Intel 82801DB PRO/100 VE Ethernet
100 device pci 1f.0 on # ISA/LPC bridge
101 chip superio/smsc/smscsuperio # Super I/O
102 device pnp 2e.0 off # Floppy
107 device pnp 2e.3 on # Parallel port
112 device pnp 2e.4 on # Com1
116 device pnp 2e.5 on # Com2 / IR
120 device pnp 2e.7 on # PS/2 keyboard/mouse
123 irq 0x70 = 1 # Keyboard interrupt
124 irq 0x72 = 12 # Mouse interrupt
126 device pnp 2e.9 off end # Game port
127 device pnp 2e.a on # PME
130 device pnp 2e.b off end # MPU-401
133 device pci 1f.1 on end # IDE
134 device pci 1f.3 on end # SMBus
135 device pci 1f.5 on end # AC'97 audio
136 device pci 1f.6 off end # AC'97 modem
139 device apic_cluster 0 on # APIC cluster
140 chip cpu/intel/socket_PGA370 # Low Voltage PIII Micro-FCBGA Socket 479
141 device apic 0 on end # APIC