2 ## Compute the location and size of where this firmware image
3 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
6 default ROM_SECTION_SIZE = FALLBACK_SIZE
7 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
9 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
10 default ROM_SECTION_OFFSET = 0
14 ## Compute the start location and size size of
15 ## The linuxBIOS bootloader.
17 default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
18 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
21 ## Compute where this copy of linuxBIOS will start in the boot rom
23 default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
26 ## Compute a range of ROM that can cached to speed up linuxBIOS,
29 ## XIP_ROM_SIZE must be a power of 2.
30 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
32 default XIP_ROM_SIZE=65536
33 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
36 ## Set all of the defaults for an x86 architecture
42 ## Build the objects we have code for in this directory.
46 if HAVE_PIRQ_TABLE object irq_tables.o end
53 depends "$(MAINBOARD)/failover.c ./romcc"
54 action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
57 makerule ./failover.inc
58 depends "$(MAINBOARD)/failover.c ./romcc"
59 action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
63 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
64 action "./romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
67 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
68 action "./romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
72 ## Build our 16 bit and 32 bit linuxBIOS entry code
74 mainboardinit cpu/x86/16bit/entry16.inc
75 mainboardinit cpu/x86/32bit/entry32.inc
76 ldscript /cpu/x86/16bit/entry16.lds
77 ldscript /cpu/x86/32bit/entry32.lds
80 ## Build our reset vector (This is where linuxBIOS is entered)
83 mainboardinit cpu/x86/16bit/reset16.inc
84 ldscript /cpu/x86/16bit/reset16.lds
86 mainboardinit cpu/x86/32bit/reset32.inc
87 ldscript /cpu/x86/32bit/reset32.lds
90 ### Should this be in the northbridge code?
91 mainboardinit arch/i386/lib/cpu_reset.inc
94 ## Include an id string (For safe flashing)
96 mainboardinit arch/i386/lib/id.inc
97 ldscript /arch/i386/lib/id.lds
100 ### This is the early phase of linuxBIOS startup
101 ### Things are delicate and we test to see if we should
102 ### failover to another image.
104 if USE_FALLBACK_IMAGE
105 ldscript /arch/i386/lib/failover.lds
106 mainboardinit ./failover.inc
110 ### O.k. We aren't just an intermediary anymore!
116 mainboardinit cpu/x86/fpu/enable_fpu.inc
117 mainboardinit cpu/x86/mmx/enable_mmx.inc
118 mainboardinit ./auto.inc
119 mainboardinit cpu/x86/mmx/disable_mmx.inc
122 ## Include the secondary Configuration files
127 chip northbridge/amd/sc520
128 device pci_domain 0 on
130 #chip southbridge/amd/sc520
131 # register "enable_usb" = "0"
132 # register "enable_native_ide" = "1"
133 # register "enable_com_ports" = "1"
134 # register "enable_keyboard" = "0"
135 # register "enable_nvram" = "1"