2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <device/device.h>
22 #include <device/pci.h>
24 #include <boot/coreboot_tables.h>
25 #include <cpu/x86/msr.h>
26 #include <cpu/amd/mtrr.h>
27 #include <device/pci_def.h>
28 #include <../southbridge/amd/sb600/sb600.h>
31 #define ADT7461_ADDRESS 0x4C
32 #define ARA_ADDRESS 0x0C /* Alert Response Address */
33 #define SMBUS_IO_BASE 0x1000
35 extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
36 extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
38 extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type,
39 uint64_t start, uint64_t size);
40 #define ADT7461_read_byte(address) \
41 do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
42 #define ARA_read_byte(address) \
43 do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address)
44 #define ADT7461_write_byte(address, val) \
45 do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
47 uint64_t uma_memory_base, uma_memory_size;
51 /***************************************************
52 * This board, the TIM-8690 has two Marvel 88e5056 PCI-E
53 * 10/100/1000 chips on board.
54 * Both of their pin PERSTn pins are connected to GPIO 5 of the
56 ****************************************************/
57 static void enable_onboard_nic()
65 printk_info("enable_onboard_nic.\n");
67 sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
69 byte= pci_cf8_conf1.read8(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn, 0x9a);
71 pci_cf8_conf1.write8(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn, 0x9a,byte);
76 pm_iowrite(0x59,byte);
79 byte = pci_cf8_conf1.read8(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn, 0xA8);
81 byte |= (1 << 1); //set bit 1 to high
82 pci_cf8_conf1.write8(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn, 0xA8, byte);
87 static void set_thermal_config()
95 ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */
96 ADT7461_write_byte(0x0C, 0x00); /* Local Temperature Low limit */
97 ADT7461_write_byte(0x0D, 0x50); /* External Temperature Hight limit High Byte */
98 ADT7461_write_byte(0x0E, 0x00); /* External Temperature Low limit High Byte */
100 ADT7461_write_byte(0x19, 0x55); /* External THERM limit */
101 ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */
103 byte = ADT7461_read_byte(0x02); /* read status register to clear it */
104 ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */
105 printk_info("Init adt7461 end , status 0x02 %02x\n", byte);
107 /* sb600 settings for thermal config */
108 /* set SB600 GPIO 64 to GPIO with pull-up */
109 byte = pm2_ioread(0x42);
111 pm2_iowrite(0x42, byte);
113 /* set GPIO 64 to input */
114 sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
116 pci_cf8_conf1.read16(&pbus, sm_dev->bus->secondary,
117 sm_dev->path.pci.devfn, 0x56);
119 pci_cf8_conf1.write16(&pbus, sm_dev->bus->secondary,
120 sm_dev->path.pci.devfn, 0x56, word);
122 /* set GPIO 64 internal pull-up */
123 byte = pm2_ioread(0xf0);
125 pm2_iowrite(0xf0, byte);
127 /* set Talert to be active low */
128 byte = pm_ioread(0x67);
130 pm_iowrite(0x67, byte);
132 /* set Talert to generate ACPI event */
133 byte = pm_ioread(0x3c);
135 pm_iowrite(0x3c, byte);
138 /* byte = pm_ioread(0x68);
140 * pm_iowrite(0x68, byte);
142 * byte = pm_ioread(0x55);
144 * pm_iowrite(0x55, byte);
146 * byte = pm_ioread(0x67);
147 * byte &= ~( 1 << 6);
148 * pm_iowrite(0x67, byte);
152 /*************************************************
153 * enable the dedicated function in tim8690 board.
154 * This function called early than rs690_enable.
155 *************************************************/
156 void tim8690_enable(device_t dev)
158 struct mainboard_config *mainboard =
159 (struct mainboard_config *)dev->chip_info;
161 printk_info("Mainboard tim8690 Enable. dev=0x%p\n", dev);
163 #if (CONFIG_GFXUMA == 1)
166 /* TOP_MEM: the top of DRAM below 4G */
167 msr = rdmsr(TOP_MEM);
168 printk_info("%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
169 __func__, msr.lo, msr.hi);
171 /* TOP_MEM2: the top of DRAM above 4G */
172 msr2 = rdmsr(TOP_MEM2);
173 printk_info("%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
174 __func__, msr2.lo, msr2.hi);
177 case 0x10000000: /* 256M system memory */
178 uma_memory_size = 0x2000000; /* 32M recommended UMA */
181 case 0x18000000: /* 384M system memory */
182 uma_memory_size = 0x4000000; /* 64M recommended UMA */
185 case 0x20000000: /* 512M system memory */
186 uma_memory_size = 0x4000000; /* 64M recommended UMA */
189 default: /* 1GB and above system memory */
190 uma_memory_size = 0x8000000; /* 128M recommended UMA */
194 uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */
195 printk_info("%s: uma size 0x%08llx, memory start 0x%08llx\n",
196 __func__, uma_memory_size, uma_memory_base);
200 uma_memory_size = 0x8000000; /* 128M recommended UMA */
201 uma_memory_base = 0x38000000; /* 1GB system memory supposed */
204 enable_onboard_nic();
205 set_thermal_config();
208 int add_mainboard_resources(struct lb_memory *mem)
210 /* UMA is removed from system memory in the northbridge code, but
211 * in some circumstances we want the memory mentioned as reserved.
213 #if (CONFIG_GFXUMA == 1)
214 printk_info("uma_memory_base=0x%llx, uma_memory_size=0x%llx \n",
215 uma_memory_base, uma_memory_size);
216 lb_add_memory_range(mem, LB_MEM_RESERVED,
217 uma_memory_base, uma_memory_size);
222 * CONFIG_CHIP_NAME defined in Option.lb.
224 struct chip_operations mainboard_ops = {
225 CHIP_NAME("TechNexion TIM-8690 Mainboard")
226 .enable_dev = tim8690_enable,