src/mainboard/technexion/tim8690/cache_as_ram_auto.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #define ASSEMBLY 1
  21 #define __ROMCC__
  22
  23 #define RAMINIT_SYSINFO 1
  24 #define K8_SET_FIDVID 1
  25 #define QRANK_DIMM_SUPPORT 1
  26 #if CONFIG_LOGICAL_CPUS==1
  27 #define SET_NB_CFG_54 1
  28 #endif
  29
  30 #define RC0 (6<<8)
  31 #define RC1 (7<<8)
  32
  33 #define DIMM0 0x50
  34 #define DIMM1 0x51
  35
  36 #define ICS951462_ADDRESS       0x69
  37 #define SMBUS_HUB 0x71
  38
  39 #include <stdint.h>
  40 #include <device/pci_def.h>
  41 #include <arch/io.h>
  42 #include <device/pnp_def.h>
  43 #include <arch/romcc_io.h>
  44 #include <cpu/x86/lapic.h>
  45 #include "option_table.h"
  46 #include "pc80/mc146818rtc_early.c"
  47 #include "pc80/serial.c"
  48 #include "arch/i386/lib/console.c"
  49
  50 #define post_code(x) outb(x, 0x80)
  51
  52 #include <cpu/amd/model_fxx_rev.h>
  53 #include "northbridge/amd/amdk8/raminit.h"
  54 #include "cpu/amd/model_fxx/apic_timer.c"
  55 #include "lib/delay.c"
  56
  57 #if CONFIG_USE_INIT == 0
  58 #include "lib/memcpy.c"
  59 #endif
  60
  61 #include "cpu/x86/lapic/boot_cpu.c"
  62 #include "northbridge/amd/amdk8/reset_test.c"
  63 #include "northbridge/amd/amdk8/debug.c"
  64 #include "superio/ite/it8712f/it8712f_early_serial.c"
  65
  66 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  67 #include "cpu/x86/bist.h"
  68
  69 #include "northbridge/amd/amdk8/setup_resource_map.c"
  70
  71 #include "southbridge/amd/rs690/rs690_early_setup.c"
  72 #include "southbridge/amd/sb600/sb600_early_setup.c"
  73
  74 /* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
  75 static void memreset(int controllers, const struct mem_controller *ctrl)
  76 {
  77 }
  78
  79 /* called in raminit_f.c */
  80 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  81 {
  82 }
  83
  84 /*called in raminit_f.c */
  85 static inline int spd_read_byte(u32 device, u32 address)
  86 {
  87         return smbus_read_byte(device, address);
  88 }
  89
  90 #include "northbridge/amd/amdk8/amdk8.h"
  91 #include "northbridge/amd/amdk8/incoherent_ht.c"
  92 #include "northbridge/amd/amdk8/raminit.c"
  93 #include "northbridge/amd/amdk8/coherent_ht.c"
  94 #include "sdram/generic_sdram.c"
  95 #include "resourcemap.c"
  96
  97 #include "cpu/amd/dualcore/dualcore.c"
  98
  99 #include "cpu/amd/car/copy_and_run.c"
 100 #include "cpu/amd/car/post_cache_as_ram.c"
 101
 102 #include "cpu/amd/model_fxx/init_cpus.c"
 103
 104 #include "cpu/amd/model_fxx/fidvid.c"
 105
 106 #if USE_FALLBACK_IMAGE == 1
 107
 108 #include "northbridge/amd/amdk8/early_ht.c"
 109
 110 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 111 {
 112         /* Is this a cpu only reset? Is this a secondary cpu? */
 113         if ((cpu_init_detectedx) || (!boot_cpu())) {
 114                 if (last_boot_normal()) {       /* RTC already inited */
 115                         goto normal_image;
 116                 } else {
 117                         goto fallback_image;
 118                 }
 119         }
 120         /* Nothing special needs to be done to find bus 0 */
 121         /* Allow the HT devices to be found */
 122         enumerate_ht_chain();
 123
 124         /* sb600_lpc_port80(); */
 125         sb600_pci_port80();
 126
 127         /* Is this a deliberate reset by the bios */
 128         if (bios_reset_detected() && last_boot_normal()) {
 129                 goto normal_image;
 130         }
 131         /* This is the primary cpu how should I boot? */
 132         else if (do_normal_boot()) {
 133                 goto normal_image;
 134         } else {
 135                 goto fallback_image;
 136         }
 137 normal_image:
 138         post_code(0x23);
 139         __asm__ volatile ("jmp __normal_image": /* outputs */
 140                           :"a" (bist), "b"(cpu_init_detectedx)  /* inputs */);
 141
 142 fallback_image:
 143         post_code(0x25);
 144 }
 145 #endif                          /* USE_FALLBACK_IMAGE == 1 */
 146
 147 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 148
 149 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 150 {
 151
 152 #if USE_FALLBACK_IMAGE == 1
 153         failover_process(bist, cpu_init_detectedx);
 154 #endif
 155         real_main(bist, cpu_init_detectedx);
 156 }
 157
 158 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 159 {
 160         static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
 161         int needs_reset = 0;
 162         u32 bsp_apicid = 0;
 163         msr_t msr;
 164         struct cpuid_result cpuid1;
 165         struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
 166
 167
 168         if (bist == 0) {
 169                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 170         }
 171
 172         enable_rs690_dev8();
 173         sb600_lpc_init();
 174
 175         /* it8712f_enable_serial does not use its 1st parameter. */
 176         it8712f_enable_serial(0, TTYS0_BASE);
 177         it8712f_kill_watchdog();
 178         uart_init();
 179         console_init();
 180
 181         /* Halt if there was a built in self test failure */
 182         report_bist_failure(bist);
 183         printk_debug("bsp_apicid=0x%x\n", bsp_apicid);
 184
 185         setup_tim8690_resource_map();
 186
 187         setup_coherent_ht_domain();
 188
 189 #if CONFIG_LOGICAL_CPUS==1
 190         /* It is said that we should start core1 after all core0 launched */
 191         wait_all_core0_started();
 192         start_other_cores();
 193 #endif
 194         wait_all_aps_started(bsp_apicid);
 195
 196         ht_setup_chains_x(sysinfo);
 197
 198         /* run _early_setup before soft-reset. */
 199         rs690_early_setup();
 200         sb600_early_setup();
 201
 202         /* Check to see if processor is capable of changing FIDVID  */
 203         /* otherwise it will throw a GP# when reading FIDVID_STATUS */
 204         cpuid1 = cpuid(0x80000007);
 205         if( (cpuid1.edx & 0x6) == 0x6 ) {
 206
 207                 /* Read FIDVID_STATUS */
 208                 msr=rdmsr(0xc0010042);
 209                 printk_debug("begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 210
 211                 enable_fid_change();
 212                 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 213                 init_fidvid_bsp(bsp_apicid);
 214
 215                 /* show final fid and vid */
 216                 msr=rdmsr(0xc0010042);
 217                 printk_debug("end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 218
 219         } else {
 220                 printk_debug("Changing FIDVID not supported\n");
 221         }
 222
 223         needs_reset = optimize_link_coherent_ht();
 224         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 225         rs690_htinit();
 226         printk_debug("needs_reset=0x%x\n", needs_reset);
 227
 228
 229         if (needs_reset) {
 230                 print_info("ht reset -\r\n");
 231                 soft_reset();
 232         }
 233
 234         allow_all_aps_stop(bsp_apicid);
 235
 236         /* It's the time to set ctrl now; */
 237         printk_debug("sysinfo->nodes: %2x  sysinfo->ctrl: %2x  spd_addr: %2x\n",
 238                      sysinfo->nodes, sysinfo->ctrl, spd_addr);
 239         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 240         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 241
 242         rs690_before_pci_init();
 243         sb600_before_pci_init();
 244
 245         post_cache_as_ram();
 246 }