src/mainboard/technexion/tim8690/Config.lb

   1 ##
   2 ## This file is part of the coreboot project.
   3 ##
   4 ## Copyright (C) 2008 Advanced Micro Devices, Inc.
   5 ##
   6 ## This program is free software; you can redistribute it and/or modify
   7 ## it under the terms of the GNU General Public License as published by
   8 ## the Free Software Foundation; version 2 of the License.
   9 ##
  10 ## This program is distributed in the hope that it will be useful,
  11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 ## GNU General Public License for more details.
  14 ##
  15 ## You should have received a copy of the GNU General Public License
  16 ## along with this program; if not, write to the Free Software
  17 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18 ##
  19 ##
  20 ##
  21
  22 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
  23 default CONFIG_XIP_ROM_SIZE = 64 * 1024
  24 include /config/nofailovercalculation.lb
  25
  26 arch i386 end
  27
  28 ##
  29 ## Build the objects we have code for in this directory.
  30 ##
  31
  32 driver mainboard.o
  33
  34 #dir /drivers/si/3114
  35
  36 if CONFIG_GENERATE_MP_TABLE object mptable.o end
  37 if CONFIG_GENERATE_PIRQ_TABLE
  38         object get_bus_conf.o
  39         object irq_tables.o
  40 end
  41
  42 if CONFIG_GENERATE_ACPI_TABLES
  43         object acpi_tables.o
  44         object fadt.o
  45         makerule dsdt.c
  46                 depends "$(CONFIG_MAINBOARD)/acpi/*.asl"
  47                 action  "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/acpi/dsdt.asl"
  48                 action  "mv dsdt.hex dsdt.c"
  49         end
  50         object ./dsdt.o
  51 end
  52
  53         if CONFIG_USE_INIT
  54
  55                 makerule ./cache_as_ram_auto.o
  56                         depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
  57                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
  58                 end
  59
  60         else
  61
  62                 makerule ./cache_as_ram_auto.inc
  63                         depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
  64                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
  65                         action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
  66                         action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
  67                 end
  68
  69         end
  70
  71 ##
  72 ## Build our 16 bit and 32 bit coreboot entry code
  73 ##
  74 mainboardinit cpu/x86/16bit/entry16.inc
  75 mainboardinit cpu/x86/32bit/entry32.inc
  76 ldscript /cpu/x86/16bit/entry16.lds
  77         if CONFIG_USE_INIT
  78                 ldscript /cpu/x86/32bit/entry32.lds
  79         end
  80
  81         if CONFIG_USE_INIT
  82                 ldscript      /cpu/amd/car/cache_as_ram.lds
  83         end
  84
  85 ##
  86 ## Build our reset vector (This is where coreboot is entered)
  87 ##
  88 if CONFIG_USE_FALLBACK_IMAGE
  89         mainboardinit cpu/x86/16bit/reset16.inc
  90         ldscript /cpu/x86/16bit/reset16.lds
  91 else
  92         mainboardinit cpu/x86/32bit/reset32.inc
  93         ldscript /cpu/x86/32bit/reset32.lds
  94 end
  95
  96 ##
  97 ## Include an id string (For safe flashing)
  98 ##
  99 mainboardinit arch/i386/lib/id.inc
 100 ldscript /arch/i386/lib/id.lds
 101
 102         ##
 103         ## Setup Cache-As-Ram
 104         ##
 105         mainboardinit cpu/amd/car/cache_as_ram.inc
 106
 107 ###
 108 ### This is the early phase of coreboot startup
 109 ### Things are delicate and we test to see if we should
 110 ### failover to another image.
 111 ###
 112 if CONFIG_USE_FALLBACK_IMAGE
 113                 ldscript /arch/i386/lib/failover.lds
 114 end
 115
 116 ###
 117 ### O.k. We aren't just an intermediary anymore!
 118 ###
 119
 120 ##
 121 ## Setup RAM
 122 ##
 123         if CONFIG_USE_INIT
 124                 initobject cache_as_ram_auto.o
 125         else
 126                 mainboardinit ./cache_as_ram_auto.inc
 127         end
 128
 129 ##
 130 ## Include the secondary Configuration files
 131 ##
 132 config chip.h
 133
 134 #The variables belong to mainboard are defined here.
 135
 136 #Define gpp_configuration,      A=0, B=1, C=2, D=3, E=4(default)
 137 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
 138 #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
 139 #                       1: the system allows a PCIE link to be established on Dev2 or Dev3.
 140 #Define gfx_dual_slot, 0: single slot, 1: dual slot
 141 #Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
 142 #Define gfx_tmds, 0: didn't support TMDS, 1: support
 143 #Define gfx_compliance, 0: didn't support compliance, 1: support
 144 #Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
 145 #Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
 146 chip northbridge/amd/amdk8/root_complex
 147         device apic_cluster 0 on
 148                 chip cpu/amd/socket_S1G1
 149                 device apic 0 on end
 150                 end
 151         end
 152         device pci_domain 0 on
 153                 chip northbridge/amd/amdk8
 154                         device pci 18.0 on #  southbridge
 155                                 chip southbridge/amd/rs690
 156                                         device pci 0.0 on end # HT      0x7910
 157                                         device pci 1.0 on  # Internal Graphics P2P bridge 0x7912
 158                                                 device pci 5.0 on end   # Internal Graphics 0x791F
 159                                         end
 160                                         device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
 161                                         device pci 3.0 off end # PCIE P2P bridge        0x791b
 162                                         device pci 4.0 on end # PCIE P2P bridge 0x7914
 163                                         device pci 5.0 on end # PCIE P2P bridge 0x7915
 164                                         device pci 6.0 on end # PCIE P2P bridge 0x7916
 165                                         device pci 7.0 on end # PCIE P2P bridge 0x7917
 166                                         device pci 8.0 off end # NB/SB Link P2P bridge
 167                                         register "gpp_configuration" = "4"
 168                                         register "port_enable" = "0xfc"
 169                                         register "gfx_dev2_dev3" = "1"
 170                                         register "gfx_dual_slot" = "0"
 171                                         register "gfx_lane_reversal" = "0"
 172                                         register "gfx_tmds" = "0"
 173                                         register "gfx_compliance" = "0"
 174                                         register "gfx_reconfiguration" = "1"
 175                                         register "gfx_link_width" = "0"
 176                                 end
 177                                 chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus
 178                                         device pci 12.0 on end # SATA  0x4380
 179                                         device pci 13.0 on end # USB   0x4387
 180                                         device pci 13.1 on end # USB   0x4388
 181                                         device pci 13.2 on end # USB   0x4389
 182                                         device pci 13.3 on end # USB   0x438a
 183                                         device pci 13.4 on end # USB   0x438b
 184                                         device pci 13.5 on end # USB 2 0x4386
 185                                         device pci 14.0 on # SM        0x4385
 186                                                 chip drivers/generic/generic #dimm 0-0-0
 187                                                         device i2c 50 on end
 188                                                 end
 189                                                 chip drivers/generic/generic #dimm 0-0-1
 190                                                         device i2c 51 on end
 191                                                 end
 192                                                 chip drivers/generic/generic #dimm 0-1-0
 193                                                         device i2c 52 on end
 194                                                 end
 195                                                 chip drivers/generic/generic #dimm 0-1-1
 196                                                         device i2c 53 on end
 197                                                 end
 198                                         end # SM
 199                                         device pci 14.1 on end # IDE    0x438c
 200                                         device pci 14.2 on end # HDA    0x4383
 201                                         device pci 14.3 on # LPC        0x438d
 202                                                 chip superio/ite/it8712f
 203                                                         device pnp 2e.0 off #  Floppy
 204                                                                 io 0x60 = 0x3f0
 205                                                                 irq 0x70 = 6
 206                                                                 drq 0x74 = 2
 207                                                         end
 208                                                         device pnp 2e.1 on #  Com1
 209                                                                 io 0x60 = 0x3f8
 210                                                                 irq 0x70 = 4
 211                                                         end
 212                                                         device pnp 2e.2 off #  Com2
 213                                                                 io 0x60 = 0x2f8
 214                                                                 irq 0x70 = 3
 215                                                         end
 216                                                         device pnp 2e.3 off #  Parallel Port
 217                                                                 io 0x60 = 0x378
 218                                                                 irq 0x70 = 7
 219                                                         end
 220                                                         device pnp 2e.4 off end #  EC
 221                                                         device pnp 2e.5 on #  Keyboard
 222                                                                 io 0x60 = 0x60
 223                                                                 io 0x62 = 0x64
 224                                                                 irq 0x70 = 1
 225                                                         end
 226                                                         device pnp 2e.6 on #  Mouse
 227                                                                 irq 0x70 = 12
 228                                                         end
 229                                                         device pnp 2e.7 off #  GPIO, must be closed for unresolved reason.
 230                                                         end
 231                                                         device pnp 2e.8 off #  MIDI
 232                                                                 io 0x60 = 0x300
 233                                                                 irq 0x70 = 9
 234                                                         end
 235                                                         device pnp 2e.9 off #  GAME
 236                                                                 io 0x60 = 0x220
 237                                                         end
 238                                                         device pnp 2e.a off end #  CIR
 239                                                 end     #superio/ite/it8712f
 240                                         end             #LPC
 241                                         device pci 14.4 on end # PCI 0x4384
 242                                         device pci 14.5 on end # ACI 0x4382
 243                                         device pci 14.6 on end # MCI 0x438e
 244                                         register "ide0_enable" = "1"
 245                                         register "sata0_enable" = "1"
 246                                         register "hda_viddid" = "0x10ec0882"
 247                                 end     #southbridge/amd/sb600
 248                         end #  device pci 18.0
 249
 250                         device pci 18.0 on end
 251                         device pci 18.0 on end
 252                         device pci 18.1 on end
 253                         device pci 18.2 on end
 254                         device pci 18.3 on end
 255                 end             #northbridge/amd/amdk8
 256         end #pci_domain
 257 end             #northbridge/amd/amdk8/root_complex
 258