src/mainboard/technexion/tim8690/Config.lb

   1 ##
   2 ## This file is part of the coreboot project.
   3 ##
   4 ## Copyright (C) 2008 Advanced Micro Devices, Inc.
   5 ##
   6 ## This program is free software; you can redistribute it and/or modify
   7 ## it under the terms of the GNU General Public License as published by
   8 ## the Free Software Foundation; version 2 of the License.
   9 ##
  10 ## This program is distributed in the hope that it will be useful,
  11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 ## GNU General Public License for more details.
  14 ##
  15 ## You should have received a copy of the GNU General Public License
  16 ## along with this program; if not, write to the Free Software
  17 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18 ##
  19 ##
  20 ##
  21
  22
  23 ##
  24 ## Compute the location and size of where this firmware image
  25 ## (coreboot plus bootloader) will live in the boot rom chip.
  26 ##
  27 if USE_FALLBACK_IMAGE
  28         default ROM_SECTION_SIZE   = FALLBACK_SIZE
  29         default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
  30 else
  31         default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
  32         default ROM_SECTION_OFFSET = 0
  33 end
  34
  35 ##
  36 ## Compute the start location and size size of
  37 ## The coreboot bootloader.
  38 ##
  39 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
  40 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
  41
  42 ##
  43 ## Compute where this copy of coreboot will start in the boot rom
  44 ##
  45 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
  46
  47 ##
  48 ## Compute a range of ROM that can cached to speed up coreboot,
  49 ## execution speed.
  50 ##
  51 ## XIP_ROM_SIZE must be a power of 2.
  52 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
  53 ##
  54 default XIP_ROM_SIZE=65536
  55 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
  56
  57 arch i386 end
  58
  59 ##
  60 ## Build the objects we have code for in this directory.
  61 ##
  62
  63 driver mainboard.o
  64
  65 #dir /drivers/si/3114
  66
  67 if HAVE_MP_TABLE object mptable.o end
  68 if HAVE_PIRQ_TABLE
  69         object get_bus_conf.o
  70         object irq_tables.o
  71 end
  72
  73 if HAVE_ACPI_TABLES
  74         object acpi_tables.o
  75         object fadt.o
  76         makerule dsdt.c
  77                 depends "$(MAINBOARD)/acpi/*.asl"
  78                 action  "iasl -p $(PWD)/dsdt -tc $(MAINBOARD)/acpi/dsdt.asl"
  79                 action  "mv dsdt.hex dsdt.c"
  80         end
  81         object ./dsdt.o
  82 end
  83
  84 #object reset.o
  85
  86         if CONFIG_USE_INIT
  87
  88                 makerule ./cache_as_ram_auto.o
  89                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  90                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
  91                 end
  92
  93         else
  94
  95                 makerule ./cache_as_ram_auto.inc
  96                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  97                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
  98                         action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
  99                         action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
 100                 end
 101
 102         end
 103
 104 ##
 105 ## Build our 16 bit and 32 bit coreboot entry code
 106 ##
 107 mainboardinit cpu/x86/16bit/entry16.inc
 108 mainboardinit cpu/x86/32bit/entry32.inc
 109 ldscript /cpu/x86/16bit/entry16.lds
 110         if CONFIG_USE_INIT
 111                 ldscript /cpu/x86/32bit/entry32.lds
 112         end
 113
 114         if CONFIG_USE_INIT
 115                 ldscript      /cpu/amd/car/cache_as_ram.lds
 116         end
 117
 118 ##
 119 ## Build our reset vector (This is where coreboot is entered)
 120 ##
 121 if USE_FALLBACK_IMAGE
 122         mainboardinit cpu/x86/16bit/reset16.inc
 123         ldscript /cpu/x86/16bit/reset16.lds
 124 else
 125         mainboardinit cpu/x86/32bit/reset32.inc
 126         ldscript /cpu/x86/32bit/reset32.lds
 127 end
 128
 129 ##
 130 ## Include an id string (For safe flashing)
 131 ##
 132 mainboardinit arch/i386/lib/id.inc
 133 ldscript /arch/i386/lib/id.lds
 134
 135         ##
 136         ## Setup Cache-As-Ram
 137         ##
 138         mainboardinit cpu/amd/car/cache_as_ram.inc
 139
 140 ###
 141 ### This is the early phase of coreboot startup
 142 ### Things are delicate and we test to see if we should
 143 ### failover to another image.
 144 ###
 145 if USE_FALLBACK_IMAGE
 146                 ldscript /arch/i386/lib/failover.lds
 147 end
 148
 149 ###
 150 ### O.k. We aren't just an intermediary anymore!
 151 ###
 152
 153 ##
 154 ## Setup RAM
 155 ##
 156         if CONFIG_USE_INIT
 157                 initobject cache_as_ram_auto.o
 158         else
 159                 mainboardinit ./cache_as_ram_auto.inc
 160         end
 161
 162 ##
 163 ## Include the secondary Configuration files
 164 ##
 165 config chip.h
 166
 167 #The variables belong to mainboard are defined here.
 168
 169 #Define gpp_configuration,      A=0, B=1, C=2, D=3, E=4(default)
 170 #Define vga_rom_address = 0xfff80000
 171 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
 172 #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
 173 #                                          1: the system allows a PCIE link to be established on Dev2 or Dev3.
 174 #Define gfx_dual_slot, 0: single slot, 1: dual slot
 175 #Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
 176 #Define gfx_tmds, 0: didn't support TMDS, 1: support
 177 #Define gfx_compliance, 0: didn't support compliance, 1: support
 178 #Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
 179 #Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
 180 chip northbridge/amd/amdk8/root_complex
 181         device apic_cluster 0 on
 182                 chip cpu/amd/socket_S1G1
 183                 device apic 0 on end
 184                 end
 185         end
 186         device pci_domain 0 on
 187                 chip northbridge/amd/amdk8
 188                         device pci 18.0 on #  southbridge
 189                                 chip southbridge/amd/rs690
 190                                         device pci 0.0 on end # HT      0x7910
 191                                         device pci 1.0 on  # Internal Graphics P2P bridge 0x7912
 192                                                 chip drivers/pci/onboard
 193                                                         device pci 5.0 on end   # Internal Graphics 0x791F
 194                                                         register "rom_address" = "0xfff80000"
 195                                                 end
 196                                         end
 197                                         device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
 198                                         device pci 3.0 off end # PCIE P2P bridge        0x791b
 199                                         device pci 4.0 on end # PCIE P2P bridge 0x7914
 200                                         device pci 5.0 on end # PCIE P2P bridge 0x7915
 201                                         device pci 6.0 on end # PCIE P2P bridge 0x7916
 202                                         device pci 7.0 on end # PCIE P2P bridge 0x7917
 203                                         device pci 8.0 off end # NB/SB Link P2P bridge
 204                                         register "vga_rom_address" = "0xfff80000"
 205                                         register "gpp_configuration" = "4"
 206                                         register "port_enable" = "0xfc"
 207                                         register "gfx_dev2_dev3" = "1"
 208                                         register "gfx_dual_slot" = "0"
 209                                         register "gfx_lane_reversal" = "0"
 210                                         register "gfx_tmds" = "0"
 211                                         register "gfx_compliance" = "0"
 212                                         register "gfx_reconfiguration" = "1"
 213                                         register "gfx_link_width" = "0"
 214                                 end
 215                                 chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus
 216                                         device pci 12.0 on end # SATA  0x4380
 217                                         device pci 13.0 on end # USB   0x4387
 218                                         device pci 13.1 on end # USB   0x4388
 219                                         device pci 13.2 on end # USB   0x4389
 220                                         device pci 13.3 on end # USB   0x438a
 221                                         device pci 13.4 on end # USB   0x438b
 222                                         device pci 13.5 on end # USB 2 0x4386
 223                                         device pci 14.0 on # SM        0x4385
 224                                                 chip drivers/generic/generic #dimm 0-0-0
 225                                                         device i2c 50 on end
 226                                                 end
 227                                                 chip drivers/generic/generic #dimm 0-0-1
 228                                                         device i2c 51 on end
 229                                                 end
 230                                                 chip drivers/generic/generic #dimm 0-1-0
 231                                                         device i2c 52 on end
 232                                                 end
 233                                                 chip drivers/generic/generic #dimm 0-1-1
 234                                                         device i2c 53 on end
 235                                                 end
 236                                         end # SM
 237                                         device pci 14.1 on end # IDE    0x438c
 238                                         device pci 14.2 on end # HDA    0x4383
 239                                         device pci 14.3 on # LPC        0x438d
 240                                                 chip superio/ite/it8712f
 241                                                         device pnp 2e.0 off #  Floppy
 242                                                                 io 0x60 = 0x3f0
 243                                                                 irq 0x70 = 6
 244                                                                 drq 0x74 = 2
 245                                                         end
 246                                                         device pnp 2e.1 on #  Com1
 247                                                                 io 0x60 = 0x3f8
 248                                                                 irq 0x70 = 4
 249                                                         end
 250                                                         device pnp 2e.2 off #  Com2
 251                                                                 io 0x60 = 0x2f8
 252                                                                 irq 0x70 = 3
 253                                                         end
 254                                                         device pnp 2e.3 off #  Parallel Port
 255                                                                 io 0x60 = 0x378
 256                                                                 irq 0x70 = 7
 257                                                         end
 258                                                         device pnp 2e.4 off end #  EC
 259                                                         device pnp 2e.5 on #  Keyboard
 260                                                                 io 0x60 = 0x60
 261                                                                 io 0x62 = 0x64
 262                                                                 irq 0x70 = 1
 263                                                         end
 264                                                         device pnp 2e.6 on #  Mouse
 265                                                                 irq 0x70 = 12
 266                                                         end
 267                                                         device pnp 2e.7 off #  GPIO, must be closed for unresolved reason.
 268                                                         end
 269                                                         device pnp 2e.8 off #  MIDI
 270                                                                 io 0x60 = 0x300
 271                                                                 irq 0x70 = 9
 272                                                         end
 273                                                         device pnp 2e.9 off #  GAME
 274                                                                 io 0x60 = 0x220
 275                                                         end
 276                                                         device pnp 2e.a off end #  CIR
 277                                                 end     #superio/ite/it8712f
 278                                         end             #LPC
 279                                         device pci 14.4 on end # PCI 0x4384
 280                                         device pci 14.5 on end # ACI 0x4382
 281                                         device pci 14.6 on end # MCI 0x438e
 282                                         register "ide0_enable" = "1"
 283                                         register "sata0_enable" = "1"
 284                                         register "hda_viddid" = "0x10ec0882"
 285                                 end     #southbridge/amd/sb600
 286                         end #  device pci 18.0
 287
 288                         device pci 18.0 on end
 289                         device pci 18.0 on end
 290                         device pci 18.1 on end
 291                         device pci 18.2 on end
 292                         device pci 18.3 on end
 293                 end             #northbridge/amd/amdk8
 294         end #pci_domain
 295 end             #northbridge/amd/amdk8/root_complex
 296