2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <device/device.h>
22 #include <device/pci.h>
24 #include <boot/coreboot_tables.h>
25 #include <cpu/x86/msr.h>
26 #include <cpu/amd/mtrr.h>
27 #include <device/pci_def.h>
28 #include <../southbridge/amd/sb600/sb600.h>
30 #include "tn_post_code.h"
32 #define ADT7461_ADDRESS 0x4C
33 #define ARA_ADDRESS 0x0C /* Alert Response Address */
34 #define SMBUS_IO_BASE 0x1000
36 extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
37 extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
39 extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type,
40 uint64_t start, uint64_t size);
41 #define ADT7461_read_byte(address) \
42 do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
43 #define ARA_read_byte(address) \
44 do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address)
45 #define ADT7461_write_byte(address, val) \
46 do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
50 void tim5690_enable(device_t dev);
51 int add_mainboard_resources(struct lb_memory *mem);
54 uint64_t uma_memory_base, uma_memory_size;
59 static void set_thermal_config(void)
66 ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */
67 ADT7461_write_byte(0x0C, 0x00); /* Local Temperature Low limit */
68 ADT7461_write_byte(0x0D, 0x50); /* External Temperature Hight limit High Byte */
69 ADT7461_write_byte(0x0E, 0x00); /* External Temperature Low limit High Byte */
71 ADT7461_write_byte(0x19, 0x55); /* External THERM limit */
72 ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */
74 byte = ADT7461_read_byte(0x02); /* read status register to clear it */
75 ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */
76 printk_info("Init adt7461 end , status 0x02 %02x\n", byte);
78 /* sb600 settings for thermal config */
79 /* set SB600 GPIO 64 to GPIO with pull-up */
80 byte = pm2_ioread(0x42);
82 pm2_iowrite(0x42, byte);
84 /* set GPIO 64 to input */
85 sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
86 word = pci_read_config16(sm_dev, 0x56);
88 pci_write_config16(sm_dev, 0x56, word);
90 /* set GPIO 64 internal pull-up */
91 byte = pm2_ioread(0xf0);
93 pm2_iowrite(0xf0, byte);
95 /* set Talert to be active low */
96 byte = pm_ioread(0x67);
98 pm_iowrite(0x67, byte);
100 /* set Talert to generate ACPI event */
101 byte = pm_ioread(0x3c);
103 pm_iowrite(0x3c, byte);
106 /* byte = pm_ioread(0x68);
108 * pm_iowrite(0x68, byte);
110 * byte = pm_ioread(0x55);
112 * pm_iowrite(0x55, byte);
114 * byte = pm_ioread(0x67);
115 * byte &= ~( 1 << 6);
116 * pm_iowrite(0x67, byte);
120 /*************************************************
121 * enable the dedicated function in tim5690 board.
122 * This function called early than rs690_enable.
123 *************************************************/
124 void tim5690_enable(device_t dev)
126 struct mainboard_config *mainboard =
127 (struct mainboard_config *)dev->chip_info;
129 printk_info("Mainboard tim5690 Enable. dev=0x%p\n", dev);
131 #if (CONFIG_GFXUMA == 1)
134 /* TOP_MEM: the top of DRAM below 4G */
135 msr = rdmsr(TOP_MEM);
136 printk_info("%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
137 __func__, msr.lo, msr.hi);
139 /* TOP_MEM2: the top of DRAM above 4G */
140 msr2 = rdmsr(TOP_MEM2);
141 printk_info("%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
142 __func__, msr2.lo, msr2.hi);
145 case 0x10000000: /* 256M system memory */
146 uma_memory_size = 0x2000000; /* 32M recommended UMA */
149 case 0x18000000: /* 384M system memory */
150 uma_memory_size = 0x4000000; /* 64M recommended UMA */
153 case 0x20000000: /* 512M system memory */
154 uma_memory_size = 0x4000000; /* 64M recommended UMA */
157 default: /* 1GB and above system memory */
158 uma_memory_size = 0x8000000; /* 128M recommended UMA */
162 uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */
163 printk_info("%s: uma size 0x%08llx, memory start 0x%08llx\n",
164 __func__, uma_memory_size, uma_memory_base);
168 uma_memory_size = 0x8000000; /* 128M recommended UMA */
169 uma_memory_base = 0x38000000; /* 1GB system memory supposed */
172 set_thermal_config();
175 int add_mainboard_resources(struct lb_memory *mem)
177 /* UMA is removed from system memory in the northbridge code, but
178 * in some circumstances we want the memory mentioned as reserved.
180 #if (CONFIG_GFXUMA == 1)
181 printk_info("uma_memory_base=0x%llx, uma_memory_size=0x%llx \n",
182 uma_memory_base, uma_memory_size);
183 lb_add_memory_range(mem, LB_MEM_RESERVED,
184 uma_memory_base, uma_memory_size);
186 technexion_post_code(LED_MESSAGE_FINISH);
189 struct chip_operations mainboard_ops = {
190 CHIP_NAME("TechNexion TIM-5690 Mainboard")
191 .enable_dev = tim5690_enable,