2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <device/device.h>
22 #include <device/pci.h>
24 #include <boot/coreboot_tables.h>
25 #include <arch/coreboot_tables.h>
26 #include <cpu/x86/msr.h>
27 #include <cpu/amd/mtrr.h>
28 #include <device/pci_def.h>
29 #include <southbridge/amd/sb600/sb600.h>
30 #include <superio/ite/it8712f/it8712f.h>
32 #include "tn_post_code.h"
35 #define ADT7461_ADDRESS 0x4C
36 #define ARA_ADDRESS 0x0C /* Alert Response Address */
37 #define SMBUS_IO_BASE 0x1000
40 /* Video BIOS Function Extensions Specification
42 //Callback Sub-Function 00h - Get LCD Panel ID
43 #define LCD_PANEL_ID_NO 0x00 /* No LCD */
44 #define LCD_PANEL_ID_01 0x01 /* 1024x768, 24 bits, 1 channel */
45 #define LCD_PANEL_ID_02 0x02 /* 1280x1024, 24 bits, 2 channels */
46 #define LCD_PANEL_ID_03 0x03 /* 1440x900, 24 bits, 2 channels */
47 #define LCD_PANEL_ID_04 0x04 /* 1680x1050, 24 bits, 2 channels */
48 #define LCD_PANEL_ID_05 0x05 /* 1920x1200, 24 bits, 2 channels */
49 #define LCD_PANEL_ID_06 0x06 /* 1920x1080, 24 bits, 2 channels */
50 //Callback Sub-Function 05h – Select Boot-up TV Standard
51 #define TV_MODE_00 0x00 /* NTSC */
52 #define TV_MODE_01 0x01 /* PAL */
53 #define TV_MODE_02 0x02 /* PALM */
54 #define TV_MODE_03 0x03 /* PAL60 */
55 #define TV_MODE_04 0x04 /* NTSCJ */
56 #define TV_MODE_05 0x05 /* PALCN */
57 #define TV_MODE_06 0x06 /* PALN */
58 #define TV_MODE_09 0x09 /* SCART-RGB */
59 #define TV_MODE_NO 0xff /* No TV Support */
61 /* The base address is 0x2e or 0x4e, depending on config bytes. */
63 #define SIO_INDEX SIO_BASE
64 #define SIO_DATA SIO_BASE+1
66 /* Global configuration registers. */
67 #define IT8712F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
68 #define IT8712F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
69 #define IT8712F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
70 #define IT8712F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */
71 #define IT8712F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */
72 #define IT8712F_CONFIG_REG_MFC 0x2a /* Multi-function control */
73 #define IT8712F_CONFIG_REG_WATCHDOG 0x72 /* Watchdog control. */
75 #define IT8712F_CONFIGURATION_PORT 0x2e /* Write-only. */
76 #define IT8712F_SIMPLE_IO_BASE 0x200 /* Simple I/O base address */
78 int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
79 int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val);
80 #define ADT7461_read_byte(address) \
81 do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
82 #define ARA_read_byte(address) \
83 do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address)
84 #define ADT7461_write_byte(address, val) \
85 do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
87 uint64_t uma_memory_base, uma_memory_size;
89 /* The content of IT8712F_CONFIG_REG_LDN (index 0x07) must be set to the
90 LDN the register belongs to, before you can access the register. */
91 static void it8712f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
93 outb(IT8712F_CONFIG_REG_LDN, SIO_BASE);
95 outb(index, SIO_BASE);
96 outb(value, SIO_DATA);
99 static void it8712f_enter_conf(void)
101 /* Enter the configuration state (MB PnP mode). */
103 /* Perform MB PnP setup to put the SIO chip at 0x2e. */
104 /* Base address 0x2e: 0x87 0x01 0x55 0x55. */
105 /* Base address 0x4e: 0x87 0x01 0x55 0xaa. */
106 outb(0x87, IT8712F_CONFIGURATION_PORT);
107 outb(0x01, IT8712F_CONFIGURATION_PORT);
108 outb(0x55, IT8712F_CONFIGURATION_PORT);
109 outb(0x55, IT8712F_CONFIGURATION_PORT);
112 static void it8712f_exit_conf(void)
114 /* Exit the configuration state (MB PnP mode). */
115 it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02);
118 /* set thermal config
120 static void set_thermal_config(void)
127 ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */
128 ADT7461_write_byte(0x0C, 0x00); /* Local Temperature Low limit */
129 ADT7461_write_byte(0x0D, 0x50); /* External Temperature Hight limit High Byte */
130 ADT7461_write_byte(0x0E, 0x00); /* External Temperature Low limit High Byte */
132 ADT7461_write_byte(0x19, 0x55); /* External THERM limit */
133 ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */
135 byte = ADT7461_read_byte(0x02); /* read status register to clear it */
136 ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */
137 printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte);
139 /* sb600 settings for thermal config */
140 /* set SB600 GPIO 64 to GPIO with pull-up */
141 byte = pm2_ioread(0x42);
143 pm2_iowrite(0x42, byte);
145 /* set GPIO 64 to input */
146 sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
147 word = pci_read_config16(sm_dev, 0x56);
149 pci_write_config16(sm_dev, 0x56, word);
151 /* set GPIO 64 internal pull-up */
152 byte = pm2_ioread(0xf0);
154 pm2_iowrite(0xf0, byte);
156 /* set Talert to be active low */
157 byte = pm_ioread(0x67);
159 pm_iowrite(0x67, byte);
161 /* set Talert to generate ACPI event */
162 byte = pm_ioread(0x3c);
164 pm_iowrite(0x3c, byte);
167 /* byte = pm_ioread(0x68);
169 * pm_iowrite(0x68, byte);
171 * byte = pm_ioread(0x55);
173 * pm_iowrite(0x55, byte);
175 * byte = pm_ioread(0x67);
176 * byte &= ~( 1 << 6);
177 * pm_iowrite(0x67, byte);
181 /* Mainboard specific GPIO setup. */
182 void mb_gpio_init(u16 *iobase)
184 /* Init Super I/O GPIOs. */
185 it8712f_enter_conf();
186 outb(IT8712F_CONFIG_REG_LDN, SIO_INDEX);
187 outb(IT8712F_GPIO, SIO_DATA);
188 outb(0x62, SIO_INDEX);
189 outb((*iobase >> 8), SIO_DATA);
190 outb(0x63, SIO_INDEX);
191 outb((*iobase & 0xff), SIO_DATA);
195 /* The LCD's panel id seletion. */
196 void lcd_panel_id(rs690_vbios_regs *vbios_regs, u8 num_id)
200 vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_01;
203 vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_02;
206 vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_03;
209 vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_04;
212 vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_05;
215 vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_06;
218 vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_NO;
223 /*************************************************
224 * enable the dedicated function in tim5690 board.
225 * This function called early than rs690_enable.
226 *************************************************/
227 static void tim5690_enable(device_t dev)
229 struct mainboard_config *mainboard =
230 (struct mainboard_config *)dev->chip_info;
232 rs690_vbios_regs vbios_regs;
233 u16 gpio_base = IT8712F_SIMPLE_IO_BASE;
236 printk(BIOS_INFO, "Mainboard tim5690 Enable. dev=0x%p\n", dev);
238 mb_gpio_init(&gpio_base);
240 /* The LCD's panel id seletion by switch. */
241 port2 = inb(gpio_base+1);
242 lcd_panel_id(&vbios_regs, ((~port2) & 0xf));
244 vbios_regs.int15_regs.fun05_tv_standard = TV_MODE_NO;
245 vgabios_init(&vbios_regs);
247 #if (CONFIG_GFXUMA == 1)
250 /* TOP_MEM: the top of DRAM below 4G */
251 msr = rdmsr(TOP_MEM);
252 printk(BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
253 __func__, msr.lo, msr.hi);
255 /* TOP_MEM2: the top of DRAM above 4G */
256 msr2 = rdmsr(TOP_MEM2);
257 printk(BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
258 __func__, msr2.lo, msr2.hi);
261 case 0x10000000: /* 256M system memory */
262 uma_memory_size = 0x2000000; /* 32M recommended UMA */
265 case 0x18000000: /* 384M system memory */
266 uma_memory_size = 0x4000000; /* 64M recommended UMA */
269 case 0x20000000: /* 512M system memory */
270 uma_memory_size = 0x4000000; /* 64M recommended UMA */
273 default: /* 1GB and above system memory */
274 uma_memory_size = 0x8000000; /* 128M recommended UMA */
278 uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */
279 printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
280 __func__, uma_memory_size, uma_memory_base);
284 uma_memory_size = 0x8000000; /* 128M recommended UMA */
285 uma_memory_base = 0x38000000; /* 1GB system memory supposed */
288 set_thermal_config();
291 int add_mainboard_resources(struct lb_memory *mem)
293 /* UMA is removed from system memory in the northbridge code, but
294 * in some circumstances we want the memory mentioned as reserved.
296 #if (CONFIG_GFXUMA == 1)
297 printk(BIOS_INFO, "uma_memory_base=0x%llx, uma_memory_size=0x%llx \n",
298 uma_memory_base, uma_memory_size);
299 lb_add_memory_range(mem, LB_MEM_RESERVED,
300 uma_memory_base, uma_memory_size);
302 technexion_post_code(LED_MESSAGE_FINISH);
306 struct chip_operations mainboard_ops = {
307 CHIP_NAME("TechNexion TIM-5690 Mainboard")
308 .enable_dev = tim5690_enable,