src/mainboard/technexion/tim5690/cache_as_ram_auto.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #define ASSEMBLY 1
  21 #define __PRE_RAM__
  22
  23 #define RAMINIT_SYSINFO 1
  24 #define K8_SET_FIDVID 1
  25 #define QRANK_DIMM_SUPPORT 1
  26 #if CONFIG_LOGICAL_CPUS==1
  27 #define SET_NB_CFG_54 1
  28 #endif
  29
  30 #define RC0 (6<<8)
  31 #define RC1 (7<<8)
  32
  33 #define DIMM0 0x50
  34 #define DIMM1 0x51
  35
  36 #define ICS951462_ADDRESS       0x69
  37 #define SMBUS_HUB 0x71
  38
  39 #include <stdint.h>
  40 #include <string.h>
  41 #include <device/pci_def.h>
  42 #include <arch/io.h>
  43 #include <device/pnp_def.h>
  44 #include <arch/romcc_io.h>
  45 #include <cpu/x86/lapic.h>
  46 #include "option_table.h"
  47 #include "pc80/mc146818rtc_early.c"
  48 #include "pc80/serial.c"
  49 #include "arch/i386/lib/console.c"
  50
  51 #define post_code(x) outb(x, 0x80)
  52
  53 #include <cpu/amd/model_fxx_rev.h>
  54 #include "northbridge/amd/amdk8/raminit.h"
  55 #include "cpu/amd/model_fxx/apic_timer.c"
  56 #include "lib/delay.c"
  57
  58 #include "cpu/x86/lapic/boot_cpu.c"
  59 #include "northbridge/amd/amdk8/reset_test.c"
  60 #include "northbridge/amd/amdk8/debug.c"
  61 #include "superio/ite/it8712f/it8712f_early_serial.c"
  62
  63 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  64 #include "cpu/x86/bist.h"
  65
  66 #include "northbridge/amd/amdk8/setup_resource_map.c"
  67
  68 #include "southbridge/amd/rs690/rs690_early_setup.c"
  69 #include "southbridge/amd/sb600/sb600_early_setup.c"
  70
  71 /* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
  72 static void memreset(int controllers, const struct mem_controller *ctrl)
  73 {
  74 }
  75
  76 /* called in raminit_f.c */
  77 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  78 {
  79 }
  80
  81 /*called in raminit_f.c */
  82 static inline int spd_read_byte(u32 device, u32 address)
  83 {
  84         return smbus_read_byte(device, address);
  85 }
  86
  87 #include "northbridge/amd/amdk8/amdk8.h"
  88 #include "northbridge/amd/amdk8/incoherent_ht.c"
  89 #include "northbridge/amd/amdk8/raminit_f.c"
  90 #include "northbridge/amd/amdk8/coherent_ht.c"
  91 #include "lib/generic_sdram.c"
  92 #include "resourcemap.c"
  93
  94 #include "cpu/amd/dualcore/dualcore.c"
  95
  96 #include "cpu/amd/car/copy_and_run.c"
  97 #include "cpu/amd/car/post_cache_as_ram.c"
  98
  99 #include "cpu/amd/model_fxx/init_cpus.c"
 100
 101 #include "cpu/amd/model_fxx/fidvid.c"
 102
 103 #include "tn_post_code.c"
 104 #include "speaker.c"
 105
 106
 107 #if CONFIG_USE_FALLBACK_IMAGE == 1
 108
 109 #include "northbridge/amd/amdk8/early_ht.c"
 110
 111 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 112 {
 113         /* Is this a cpu only reset? Is this a secondary cpu? */
 114         if ((cpu_init_detectedx) || (!boot_cpu())) {
 115                 if (last_boot_normal()) {       /* RTC already inited */
 116                         goto normal_image;
 117                 } else {
 118                         goto fallback_image;
 119                 }
 120         }
 121         /* Nothing special needs to be done to find bus 0 */
 122         /* Allow the HT devices to be found */
 123         enumerate_ht_chain();
 124
 125         /* sb600_lpc_port80(); */
 126         sb600_pci_port80();
 127
 128         /* Is this a deliberate reset by the bios */
 129         if (bios_reset_detected() && last_boot_normal()) {
 130                 goto normal_image;
 131         }
 132         /* This is the primary cpu how should I boot? */
 133         else if (do_normal_boot()) {
 134                 goto normal_image;
 135         } else {
 136                 goto fallback_image;
 137         }
 138 normal_image:
 139         post_code(0x23);
 140         __asm__ volatile ("jmp __normal_image": /* outputs */
 141                           :"a" (bist), "b"(cpu_init_detectedx)  /* inputs */);
 142
 143 fallback_image:
 144         post_code(0x25);
 145 }
 146 #endif                          /* CONFIG_USE_FALLBACK_IMAGE == 1 */
 147
 148 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 149
 150 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 151 {
 152
 153 #if CONFIG_USE_FALLBACK_IMAGE == 1
 154         failover_process(bist, cpu_init_detectedx);
 155 #endif
 156         real_main(bist, cpu_init_detectedx);
 157 }
 158
 159 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 160 {
 161         static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
 162         int needs_reset = 0;
 163         u32 bsp_apicid = 0;
 164         msr_t msr;
 165         struct cpuid_result cpuid1;
 166         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 167
 168         technexion_post_code_init();
 169         technexion_post_code(LED_MESSAGE_START);
 170
 171         if (bist == 0) {
 172                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 173         }
 174
 175         enable_rs690_dev8();
 176         sb600_lpc_init();
 177
 178         /* it8712f_enable_serial does not use its 1st parameter. */
 179         it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
 180         it8712f_kill_watchdog();
 181         uart_init();
 182         console_init();
 183
 184         /* Halt if there was a built in self test failure */
 185         report_bist_failure(bist);
 186         printk_debug("bsp_apicid=0x%x\n", bsp_apicid);
 187
 188         setup_tim5690_resource_map();
 189
 190         setup_coherent_ht_domain();
 191
 192 #if CONFIG_LOGICAL_CPUS==1
 193         /* It is said that we should start core1 after all core0 launched */
 194         wait_all_core0_started();
 195         start_other_cores();
 196 #endif
 197         wait_all_aps_started(bsp_apicid);
 198
 199         ht_setup_chains_x(sysinfo);
 200
 201         /* run _early_setup before soft-reset. */
 202         rs690_early_setup();
 203         sb600_early_setup();
 204
 205         /* Check to see if processor is capable of changing FIDVID  */
 206         /* otherwise it will throw a GP# when reading FIDVID_STATUS */
 207         cpuid1 = cpuid(0x80000007);
 208         if( (cpuid1.edx & 0x6) == 0x6 ) {
 209
 210                 /* Read FIDVID_STATUS */
 211                 msr=rdmsr(0xc0010042);
 212                 printk_debug("begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 213
 214                 enable_fid_change();
 215                 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 216                 init_fidvid_bsp(bsp_apicid);
 217
 218                 /* show final fid and vid */
 219                 msr=rdmsr(0xc0010042);
 220                 printk_debug("end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 221
 222         } else {
 223                 printk_debug("Changing FIDVID not supported\n");
 224         }
 225
 226         needs_reset = optimize_link_coherent_ht();
 227         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 228         rs690_htinit();
 229         printk_debug("needs_reset=0x%x\n", needs_reset);
 230
 231
 232         if (needs_reset) {
 233                 print_info("ht reset -\r\n");
 234                 soft_reset();
 235         }
 236
 237         speaker_init(255);
 238         speaker_on_nodelay();
 239
 240         allow_all_aps_stop(bsp_apicid);
 241
 242         /* It's the time to set ctrl now; */
 243         printk_debug("sysinfo->nodes: %2x  sysinfo->ctrl: %2x  spd_addr: %2x\n",
 244                      sysinfo->nodes, sysinfo->ctrl, spd_addr);
 245
 246         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 247
 248         technexion_post_code(LED_MESSAGE_RAM);
 249
 250         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 251
 252         speaker_off_nodelay();
 253
 254         rs690_before_pci_init();
 255         sb600_before_pci_init();
 256
 257         post_cache_as_ram();
 258 }