src/mainboard/supermicro/x6dhr_ig/auto.c

   1 #define ASSEMBLY 1
   2 #include <stdint.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include <stdlib.h>
   9 #include "option_table.h"
  10 #include "pc80/mc146818rtc_early.c"
  11 #include "pc80/serial.c"
  12 #include "arch/i386/lib/console.c"
  13 #include "lib/ramtest.c"
  14 #include "southbridge/intel/i82801er/i82801er_early_smbus.c"
  15 #include "northbridge/intel/e7520/raminit.h"
  16 #include "superio/winbond/w83627hf/w83627hf.h"
  17 #include "cpu/x86/lapic/boot_cpu.c"
  18 #include "cpu/x86/mtrr/earlymtrr.c"
  19 #include "debug.c"
  20 #include "watchdog.c"
  21 #include "reset.c"
  22 #include "x6dhr_fixups.c"
  23 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
  24 #include "northbridge/intel/e7520/memory_initialized.c"
  25 #include "cpu/x86/bist.h"
  26
  27
  28 #define SIO_GPIO_BASE 0x680
  29 #define SIO_XBUS_BASE 0x4880
  30
  31 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  32 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, W83627HF_SP2)
  33
  34 #define DEVPRES_CONFIG  ( \
  35         DEVPRES_D0F0 | \
  36         DEVPRES_D1F0 | \
  37         DEVPRES_D2F0 | \
  38         DEVPRES_D3F0 | \
  39         DEVPRES_D4F0 | \
  40         DEVPRES_D6F0 | \
  41         0 )
  42 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
  43
  44 #define RECVENA_CONFIG  0x0808090a
  45 #define RECVENB_CONFIG  0x0808090a
  46
  47 #if 0
  48 static void hard_reset(void)
  49 {
  50         /* enable cf9 */
  51         pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
  52         /* reset */
  53         outb(0x0e, 0x0cf9);
  54 }
  55 #endif
  56
  57 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  58 {
  59         /* nothing to do */
  60 }
  61 static inline int spd_read_byte(unsigned device, unsigned address)
  62 {
  63         return smbus_read_byte(device, address);
  64 }
  65
  66 #include "northbridge/intel/e7520/raminit.c"
  67 #include "lib/generic_sdram.c"
  68
  69
  70 static void main(unsigned long bist)
  71 {
  72         /*
  73          *
  74          *
  75          */
  76         static const struct mem_controller mch[] = {
  77                 {
  78                         .node_id = 0,
  79                         .f0 = PCI_DEV(0, 0x00, 0),
  80                         .f1 = PCI_DEV(0, 0x00, 1),
  81                         .f2 = PCI_DEV(0, 0x00, 2),
  82                         .f3 = PCI_DEV(0, 0x00, 3),
  83                         .channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, },
  84                         .channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, },
  85                 }
  86         };
  87
  88         if (bist == 0) {
  89                 /* Skip this if there was a built in self test failure */
  90                 early_mtrr_init();
  91                 if (memory_initialized()) {
  92                         asm volatile ("jmp __cpu_reset");
  93                 }
  94         }
  95         /* Setup the console */
  96         outb(0x87,0x2e);
  97         outb(0x87,0x2e);
  98         pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6));
  99         w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
 100         uart_init();
 101         console_init();
 102
 103         /* Halt if there was a built in self test failure */
 104 //      report_bist_failure(bist);
 105
 106         /* MOVE ME TO A BETTER LOCATION !!! */
 107         /* config LPC decode for flash memory access */
 108         device_t dev;
 109         dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
 110         if (dev == PCI_DEV_INVALID) {
 111                 die("Missing ich5?");
 112         }
 113         pci_write_config32(dev, 0xe8, 0x00000000);
 114         pci_write_config8(dev, 0xf0, 0x00);
 115
 116 #if 0
 117         display_cpuid_update_microcode();
 118 #endif
 119 #if 0
 120         print_pci_devices();
 121 #endif
 122 #if 1
 123         enable_smbus();
 124 #endif
 125 #if 0
 126 //      dump_spd_registers(&cpu[0]);
 127         int i;
 128         for(i = 0; i < 1; i++) {
 129                 dump_spd_registers();
 130         }
 131 #endif
 132         disable_watchdogs();
 133 //      dump_ipmi_registers();
 134         mainboard_set_e7520_leds();
 135 //      memreset_setup();
 136         sdram_initialize(ARRAY_SIZE(mch), mch);
 137 #if 1
 138         dump_pci_devices();
 139 #endif
 140 #if 0
 141         dump_pci_device(PCI_DEV(0, 0x00, 0));
 142         dump_bar14(PCI_DEV(0, 0x00, 0));
 143 #endif
 144
 145 #if 0 // temporarily disabled
 146         /* Check the first 1M */
 147 //      ram_check(0x00000000, 0x000100000);
 148 //      ram_check(0x00000000, 0x000a0000);
 149 //      ram_check(0x00100000, 0x01000000);
 150         ram_check(0x00100000, 0x00100100);
 151         /* check the first 1M in the 3rd Gig */
 152 //      ram_check(0x30100000, 0x31000000);
 153 #endif
 154 #if 0
 155         ram_check(0x00000000, 0x02000000);
 156 #endif
 157
 158 #if 0
 159         while(1) {
 160                 hlt();
 161         }
 162 #endif
 163 }