src/mainboard/supermicro/x6dhe_g2/romstage.c

   1 #include <stdint.h>
   2 #include <device/pci_def.h>
   3 #include <arch/io.h>
   4 #include <device/pnp_def.h>
   5 #include <arch/romcc_io.h>
   6 #include <cpu/x86/lapic.h>
   7 #include <stdlib.h>
   8 #include <console/console.h>
   9 #include "lib/ramtest.c"
  10 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
  11 #include "northbridge/intel/e7520/raminit.h"
  12 #include "superio/nsc/pc87427/pc87427.h"
  13 #include "cpu/x86/lapic/boot_cpu.c"
  14 #include "cpu/x86/mtrr/earlymtrr.c"
  15 #include "debug.c"
  16 #include "watchdog.c"
  17 #include "reset.c"
  18 #include "x6dhe_g2_fixups.c"
  19 #include "superio/nsc/pc87427/pc87427_early_init.c"
  20 #include "northbridge/intel/e7520/memory_initialized.c"
  21 #include "cpu/x86/bist.h"
  22
  23 #define SIO_GPIO_BASE 0x680
  24 #define SIO_XBUS_BASE 0x4880
  25
  26 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC87427_SP1)
  27 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, PC87427_SP2)
  28
  29 #define DEVPRES_CONFIG  ( \
  30         DEVPRES_D1F0 | \
  31         DEVPRES_D2F0 | \
  32         DEVPRES_D3F0 | \
  33         DEVPRES_D4F0 | \
  34         DEVPRES_D6F0 | \
  35         0 )
  36 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
  37
  38 #define RECVENA_CONFIG  0x0708090a
  39 #define RECVENB_CONFIG  0x0708090a
  40
  41 static inline int spd_read_byte(unsigned device, unsigned address)
  42 {
  43         return smbus_read_byte(device, address);
  44 }
  45
  46 #include "northbridge/intel/e7520/raminit.c"
  47 #include "lib/generic_sdram.c"
  48 #include "arch/i386/lib/stages.c"
  49
  50 static void main(unsigned long bist)
  51 {
  52         /*
  53          *
  54          *
  55          */
  56         static const struct mem_controller mch[] = {
  57                 {
  58                         .node_id = 0,
  59                         /*
  60                         .f0 = PCI_DEV(0, 0x00, 0),
  61                         .f1 = PCI_DEV(0, 0x00, 1),
  62                         .f2 = PCI_DEV(0, 0x00, 2),
  63                         .f3 = PCI_DEV(0, 0x00, 3),
  64                         */
  65                         .channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, },
  66                         .channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, },
  67
  68                 }
  69         };
  70
  71         if (bist == 0) {
  72                 /* Skip this if there was a built in self test failure */
  73                 early_mtrr_init();
  74                 if (memory_initialized()) {
  75                         skip_romstage();
  76                 }
  77         }
  78         /* Setup the console */
  79         outb(0x87,0x2e);
  80         outb(0x87,0x2e);
  81         pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6));
  82         pc87427_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
  83         uart_init();
  84         console_init();
  85
  86         /* Halt if there was a built in self test failure */
  87 //      report_bist_failure(bist);
  88
  89         /* MOVE ME TO A BETTER LOCATION !!! */
  90         /* config LPC decode for flash memory access */
  91         device_t dev;
  92         dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
  93         if (dev == PCI_DEV_INVALID) {
  94                 die("Missing ich5r?");
  95         }
  96         pci_write_config32(dev, 0xe8, 0x00000000);
  97         pci_write_config8(dev, 0xf0, 0x00);
  98
  99 #if 0
 100         display_cpuid_update_microcode();
 101 #endif
 102 #if 0
 103         print_pci_devices();
 104 #endif
 105 #if 1
 106         enable_smbus();
 107 #endif
 108 #if 0
 109 //      dump_spd_registers(&cpu[0]);
 110         int i;
 111         for(i = 0; i < 1; i++) {
 112                 dump_spd_registers();
 113         }
 114 #endif
 115         disable_watchdogs();
 116 //      dump_ipmi_registers();
 117 //      mainboard_set_e7520_leds();
 118         sdram_initialize(ARRAY_SIZE(mch), mch);
 119 #if 0
 120         dump_pci_devices();
 121 #endif
 122 #if 1
 123         dump_pci_device(PCI_DEV(0, 0x00, 0));
 124         //dump_bar14(PCI_DEV(0, 0x00, 0));
 125 #endif
 126
 127 #if 0 // temporarily disabled
 128         /* Check the first 1M */
 129 //      ram_check(0x00000000, 0x000100000);
 130 //      ram_check(0x00000000, 0x000a0000);
 131         ram_check(0x00100000, 0x01000000);
 132         /* check the first 1M in the 3rd Gig */
 133         ram_check(0x30100000, 0x31000000);
 134 #endif
 135 #if 0
 136         ram_check(0x00000000, 0x02000000);
 137 #endif
 138
 139 #if 0
 140         while(1) {
 141                 hlt();
 142         }
 143 #endif
 144 }
 145