src/mainboard/supermicro/x6dhe_g2/auto.updated.c

   1 #define ASSEMBLY 1
   2 #include <stdint.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include "option_table.h"
   9 #include "pc80/mc146818rtc_early.c"
  10 #include "pc80/serial.c"
  11 #include "arch/i386/lib/console.c"
  12 #include "ram/ramtest.c"
  13 #include "southbridge/intel/esb6300/esb6300_early_smbus.c"
  14 #include "northbridge/intel/e7520/raminit.h"
  15 #include "superio/winbond/w83627hf/w83627hf.h"
  16 #include "cpu/x86/lapic/boot_cpu.c"
  17 #include "cpu/x86/mtrr/earlymtrr.c"
  18 #include "debug.c"
  19 #include "watchdog.c"
  20 #include "reset.c"
  21 #include "x6dhe_g_fixups.c"
  22 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
  23 #include "northbridge/intel/e7520/memory_initialized.c"
  24 #include "cpu/x86/bist.h"
  25
  26
  27 #define SIO_GPIO_BASE 0x680
  28 #define SIO_XBUS_BASE 0x4880
  29
  30 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  31 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, W83627HF_SP2)
  32
  33 #define DEVPRES_CONFIG  ( \
  34         DEVPRES_D1F0 | \
  35         DEVPRES_D2F0 | \
  36         DEVPRES_D3F0 | \
  37         DEVPRES_D4F0 | \
  38         DEVPRES_D6F0 | \
  39         0 )
  40 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
  41
  42 #define RECVENA_CONFIG  0x0708090a
  43 #define RECVENB_CONFIG  0x0708090a
  44
  45 //void udelay(int usecs)
  46 //{
  47 //        int i;
  48 //        for(i = 0; i < usecs; i++)
  49 //                outb(i&0xff, 0x80);
  50 //}
  51
  52 #if 0
  53 static void hard_reset(void)
  54 {
  55         /* enable cf9 */
  56         pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
  57         /* reset */
  58         outb(0x0e, 0x0cf9);
  59 }
  60 #endif
  61
  62 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  63 {
  64         /* nothing to do */
  65 }
  66 static inline int spd_read_byte(unsigned device, unsigned address)
  67 {
  68         return smbus_read_byte(device, address);
  69 }
  70
  71 #include "northbridge/intel/e7520/raminit.c"
  72 #include "sdram/generic_sdram.c"
  73
  74
  75 static void main(unsigned long bist)
  76 {
  77         /*
  78          *
  79          *
  80          */
  81         static const struct mem_controller mch[] = {
  82                 {
  83                         .node_id = 0,
  84                         .f0 = PCI_DEV(0, 0x00, 0),
  85                         .f1 = PCI_DEV(0, 0x00, 1),
  86                         .f2 = PCI_DEV(0, 0x00, 2),
  87                         .f3 = PCI_DEV(0, 0x00, 3),
  88                         .channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, },
  89                         .channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, },
  90
  91                 }
  92         };
  93
  94         if (bist == 0) {
  95                 /* Skip this if there was a built in self test failure */
  96                 early_mtrr_init();
  97                 if (memory_initialized()) {
  98                         asm volatile ("jmp __cpu_reset");
  99                 }
 100         }
 101         /* Setup the console */
 102         outb(0x87,0x2e);
 103         outb(0x87,0x2e);
 104         pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6));
 105         w83627hf_enable_dev(CONSOLE_SERIAL_DEV, TTYS0_BASE);
 106         uart_init();
 107         console_init();
 108
 109         /* Halt if there was a built in self test failure */
 110 //      report_bist_failure(bist);
 111
 112         /* MOVE ME TO A BETTER LOCATION !!! */
 113         /* config LPC decode for flash memory access */
 114         device_t dev;
 115         dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
 116         if (dev == PCI_DEV_INVALID) {
 117                 die("Missing esb6300?");
 118         }
 119         pci_write_config32(dev, 0xe8, 0x00000000);
 120         pci_write_config8(dev, 0xf0, 0x00);
 121
 122 #if 0
 123         display_cpuid_update_microcode();
 124 #endif
 125 #if 0
 126         print_pci_devices();
 127 #endif
 128 #if 1
 129         enable_smbus();
 130 #endif
 131 #if 0
 132 //      dump_spd_registers(&cpu[0]);
 133         int i;
 134         for(i = 0; i < 1; i++) {
 135                 dump_spd_registers();
 136         }
 137 #endif
 138         disable_watchdogs();
 139 //      dump_ipmi_registers();
 140 //      mainboard_set_e7520_leds();
 141 //      memreset_setup();
 142         sdram_initialize(sizeof(mch)/sizeof(mch[0]), mch);
 143 #if 0
 144         dump_pci_devices();
 145 #endif
 146 #if 1
 147         dump_pci_device(PCI_DEV(0, 0x00, 0));
 148         //dump_bar14(PCI_DEV(0, 0x00, 0));
 149 #endif
 150
 151 #if 0 // temporarily disabled
 152         /* Check the first 1M */
 153 //      ram_check(0x00000000, 0x000100000);
 154 //      ram_check(0x00000000, 0x000a0000);
 155         ram_check(0x00100000, 0x01000000);
 156         /* check the first 1M in the 3rd Gig */
 157         ram_check(0x30100000, 0x31000000);
 158 #endif
 159 #if 0
 160         ram_check(0x00000000, 0x02000000);
 161 #endif
 162
 163 #if 0
 164         while(1) {
 165                 hlt();
 166         }
 167 #endif
 168 }