3 uses USE_FALLBACK_IMAGE
4 uses HAVE_FALLBACK_BOOT
8 uses CONFIG_LOGICAL_CPUS
17 uses ROM_SECTION_OFFSET
18 uses CONFIG_ROM_PAYLOAD
19 uses CONFIG_ROM_PAYLOAD_START
20 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
28 uses LB_CKS_RANGE_START
32 uses MAINBOARD_PART_NUMBER
34 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
35 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
36 uses LINUXBIOS_EXTRA_VERSION
37 uses CONFIG_UDELAY_TSC
38 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
41 uses CONFIG_CONSOLE_SERIAL8250
45 uses DEFAULT_CONSOLE_LOGLEVEL
46 uses MAXIMUM_CONSOLE_LOGLEVEL
47 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
48 uses CONFIG_CONSOLE_BTEXT
60 ## ROM_SIZE is the size of boot ROM that this board will use.
62 default ROM_SIZE=1048576
65 ## Build code for the fallback boot
67 default HAVE_FALLBACK_BOOT=1
70 ## Delay timer options
73 default CONFIG_UDELAY_TSC=1
74 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
77 ## Build code to reset the motherboard from linuxBIOS
79 default HAVE_HARD_RESET=1
82 ## Build code to export a programmable irq routing table
84 default HAVE_PIRQ_TABLE=1
85 default IRQ_SLOT_COUNT=16
88 ## Build code to export an x86 MP table
89 ## Useful for specifying IRQ routing values
91 default HAVE_MP_TABLE=1
94 ## Build code to export a CMOS option table
96 default HAVE_OPTION_TABLE=1
99 ## Move the default LinuxBIOS cmos range off of AMD RTC registers
101 default LB_CKS_RANGE_START=49
102 default LB_CKS_RANGE_END=122
103 default LB_CKS_LOC=123
106 ## Build code for SMP support
107 ## Only worry about 2 micro processors
110 default CONFIG_MAX_CPUS=4
111 default CONFIG_LOGICAL_CPUS=0
114 ## Build code to setup a generic IOAPIC
116 default CONFIG_IOAPIC=1
119 ## Clean up the motherboard id strings
121 default MAINBOARD_PART_NUMBER="X6DHE_g"
122 default MAINBOARD_VENDOR= "Supermicro"
123 default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9
124 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6080
127 ### LinuxBIOS layout values
130 ## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
131 default ROM_IMAGE_SIZE = 65536
134 ## Use a small 8K stack
136 default STACK_SIZE=0x2000
139 ## Use a small 32K heap
141 default HEAP_SIZE=0x8000
145 ### Compute the location and size of where this firmware image
146 ### (linuxBIOS plus bootloader) will live in the boot rom chip.
148 default FALLBACK_SIZE=131072
151 ## LinuxBIOS C code runs at this location in RAM
153 default _RAMBASE=0x00004000
156 ## Load the payload from the ROM
158 default CONFIG_ROM_PAYLOAD=1
162 ### Defaults of options that you may want to override in the target config file
166 ## The default compiler
168 default CC="$(CROSS_COMPILE)gcc -m32"
172 ## Disable the gdb stub by default
174 default CONFIG_GDB_STUB=0
177 ## The Serial Console
180 # To Enable the Serial Console
181 default CONFIG_CONSOLE_SERIAL8250=1
183 ## Select the serial console baud rate
184 default TTYS0_BAUD=115200
185 #default TTYS0_BAUD=57600
186 #default TTYS0_BAUD=38400
187 #default TTYS0_BAUD=19200
188 #default TTYS0_BAUD=9600
189 #default TTYS0_BAUD=4800
190 #default TTYS0_BAUD=2400
191 #default TTYS0_BAUD=1200
193 # Select the serial console base port
194 default TTYS0_BASE=0x3f8
196 # Select the serial protocol
197 # This defaults to 8 data bits, 1 stop bit, and no parity
198 default TTYS0_LCS=0x3
201 ### Select the linuxBIOS loglevel
203 ## EMERG 1 system is unusable
204 ## ALERT 2 action must be taken immediately
205 ## CRIT 3 critical conditions
206 ## ERR 4 error conditions
207 ## WARNING 5 warning conditions
208 ## NOTICE 6 normal but significant condition
209 ## INFO 7 informational
210 ## DEBUG 8 debug-level messages
211 ## SPEW 9 Way too many details
213 ## Request this level of debugging output
214 default DEFAULT_CONSOLE_LOGLEVEL=8
215 ## At a maximum only compile in this level of debugging
216 default MAXIMUM_CONSOLE_LOGLEVEL=8
219 ## Select power on after power fail setting
220 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
223 ## Don't enable the btext console
225 default CONFIG_CONSOLE_BTEXT=0