src/mainboard/supermicro/x6dai_g/romstage.c

   1 #include <stdint.h>
   2 #include <device/pci_def.h>
   3 #include <arch/io.h>
   4 #include <device/pnp_def.h>
   5 #include <arch/romcc_io.h>
   6 #include <cpu/x86/lapic.h>
   7 #include <stdlib.h>
   8 #include "option_table.h"
   9 #include "pc80/mc146818rtc_early.c"
  10 #include "pc80/serial.c"
  11 #include "console/console.c"
  12 #include "lib/ramtest.c"
  13 #include "southbridge/intel/esb6300/esb6300_early_smbus.c"
  14 #include "northbridge/intel/e7525/raminit.h"
  15 #include "superio/winbond/w83627hf/w83627hf.h"
  16 #include "cpu/x86/lapic/boot_cpu.c"
  17 #include "cpu/x86/mtrr/earlymtrr.c"
  18 #include "debug.c"
  19 #include "watchdog.c"
  20 #include "reset.c"
  21 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
  22 #include "northbridge/intel/e7525/memory_initialized.c"
  23 #include "cpu/x86/bist.h"
  24
  25 #define SIO_GPIO_BASE 0x680
  26 #define SIO_XBUS_BASE 0x4880
  27
  28 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  29 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, W83627HF_SP2)
  30
  31 #define DEVPRES_CONFIG  ( \
  32         DEVPRES_D1F0 | \
  33         DEVPRES_D2F0 | \
  34         DEVPRES_D3F0 | \
  35         DEVPRES_D4F0 | \
  36         DEVPRES_D6F0 | \
  37         0 )
  38 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
  39
  40 #define RECVENA_CONFIG  0x0808090a
  41 #define RECVENB_CONFIG  0x0808090a
  42
  43 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  44 {
  45         /* nothing to do */
  46 }
  47 static inline int spd_read_byte(unsigned device, unsigned address)
  48 {
  49         return smbus_read_byte(device, address);
  50 }
  51
  52 #include "northbridge/intel/e7525/raminit.c"
  53 #include "lib/generic_sdram.c"
  54 #include "arch/i386/lib/stages.c"
  55
  56 static void main(unsigned long bist)
  57 {
  58         /*
  59          *
  60          *
  61          */
  62         static const struct mem_controller mch[] = {
  63                 {
  64                         .node_id = 0,
  65                         .f0 = PCI_DEV(0, 0x00, 0),
  66                         .f1 = PCI_DEV(0, 0x00, 1),
  67                         .f2 = PCI_DEV(0, 0x00, 2),
  68                         .f3 = PCI_DEV(0, 0x00, 3),
  69                         .channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, },
  70                         .channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, },
  71                 }
  72         };
  73
  74         if (bist == 0) {
  75                 /* Skip this if there was a built in self test failure */
  76                 early_mtrr_init();
  77                 if (memory_initialized()) {
  78                         skip_romstage();
  79                 }
  80         }
  81         /* Setup the console */
  82         outb(0x87,0x2e);
  83         outb(0x87,0x2e);
  84         pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6));
  85         w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
  86         uart_init();
  87         console_init();
  88
  89         /* MOVE ME TO A BETTER LOCATION !!! */
  90         /* config LPC decode for flash memory access */
  91         device_t dev;
  92         dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
  93         if (dev == PCI_DEV_INVALID) {
  94                 die("Missing 6300ESB?");
  95         }
  96         pci_write_config32(dev, 0xe8, 0x00000000);
  97         pci_write_config8(dev, 0xf0, 0x00);
  98
  99 #if 0
 100         display_cpuid_update_microcode();
 101 #endif
 102 #if 0
 103         print_pci_devices();
 104 #endif
 105 #if 1
 106         enable_smbus();
 107 #endif
 108 #if 0
 109         int i;
 110         for(i = 0; i < 1; i++) {
 111                 dump_spd_registers();
 112         }
 113 #endif
 114         disable_watchdogs();
 115         sdram_initialize(ARRAY_SIZE(mch), mch);
 116 #if 1
 117         dump_pci_device(PCI_DEV(0, 0x00, 0));
 118 //      dump_bar14(PCI_DEV(0, 0x00, 0));
 119 #endif
 120
 121 #if 0 // temporarily disabled
 122         /* Check the first 1M */
 123 //      ram_check(0x00000000, 0x000100000);
 124 //      ram_check(0x00000000, 0x000a0000);
 125         ram_check(0x00100000, 0x01000000);
 126         /* check the first 1M in the 3rd Gig */
 127         ram_check(0x30100000, 0x31000000);
 128 #endif
 129 #if 0
 130         ram_check(0x00000000, 0x02000000);
 131 #endif
 132
 133 #if 0
 134         while(1) {
 135                 hlt();
 136         }
 137 #endif
 138 }
 139