src/mainboard/supermicro/x6dai_g/romstage.c

   1 #include <stdint.h>
   2 #include <device/pci_def.h>
   3 #include <arch/io.h>
   4 #include <device/pnp_def.h>
   5 #include <arch/romcc_io.h>
   6 #include <cpu/x86/lapic.h>
   7 #include <stdlib.h>
   8 #include "option_table.h"
   9 #include "pc80/mc146818rtc_early.c"
  10 #include <console/console.h>
  11 #include "lib/ramtest.c"
  12 #include "pc80/udelay_io.c"
  13 #include "lib/delay.c"
  14 #include "southbridge/intel/esb6300/esb6300_early_smbus.c"
  15 #include "northbridge/intel/e7525/raminit.h"
  16 #include "superio/winbond/w83627hf/w83627hf.h"
  17 #include "cpu/x86/lapic/boot_cpu.c"
  18 #include "cpu/x86/mtrr/earlymtrr.c"
  19 #include "debug.c"
  20 #include "watchdog.c"
  21 #include "reset.c"
  22 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
  23 #include "northbridge/intel/e7525/memory_initialized.c"
  24 #include "cpu/x86/bist.h"
  25
  26 #define SIO_GPIO_BASE 0x680
  27 #define SIO_XBUS_BASE 0x4880
  28
  29 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  30 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, W83627HF_SP2)
  31
  32 #define DEVPRES_CONFIG  ( \
  33         DEVPRES_D1F0 | \
  34         DEVPRES_D2F0 | \
  35         DEVPRES_D3F0 | \
  36         DEVPRES_D4F0 | \
  37         DEVPRES_D6F0 | \
  38         0 )
  39 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
  40
  41 #define RECVENA_CONFIG  0x0808090a
  42 #define RECVENB_CONFIG  0x0808090a
  43
  44 static inline int spd_read_byte(unsigned device, unsigned address)
  45 {
  46         return smbus_read_byte(device, address);
  47 }
  48
  49 #include "northbridge/intel/e7525/raminit.c"
  50 #include "lib/generic_sdram.c"
  51 #include "arch/i386/lib/stages.c"
  52
  53 static void main(unsigned long bist)
  54 {
  55         /*
  56          *
  57          *
  58          */
  59         static const struct mem_controller mch[] = {
  60                 {
  61                         .node_id = 0,
  62                         .f0 = PCI_DEV(0, 0x00, 0),
  63                         .f1 = PCI_DEV(0, 0x00, 1),
  64                         .f2 = PCI_DEV(0, 0x00, 2),
  65                         .f3 = PCI_DEV(0, 0x00, 3),
  66                         .channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, },
  67                         .channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, },
  68                 }
  69         };
  70
  71         if (bist == 0) {
  72                 /* Skip this if there was a built in self test failure */
  73                 early_mtrr_init();
  74                 if (memory_initialized()) {
  75                         skip_romstage();
  76                 }
  77         }
  78         /* Setup the console */
  79         outb(0x87,0x2e);
  80         outb(0x87,0x2e);
  81         pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6));
  82         w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
  83         uart_init();
  84         console_init();
  85
  86         /* MOVE ME TO A BETTER LOCATION !!! */
  87         /* config LPC decode for flash memory access */
  88         device_t dev;
  89         dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
  90         if (dev == PCI_DEV_INVALID) {
  91                 die("Missing 6300ESB?");
  92         }
  93         pci_write_config32(dev, 0xe8, 0x00000000);
  94         pci_write_config8(dev, 0xf0, 0x00);
  95
  96 #if 0
  97         display_cpuid_update_microcode();
  98 #endif
  99 #if 0
 100         print_pci_devices();
 101 #endif
 102 #if 1
 103         enable_smbus();
 104 #endif
 105 #if 0
 106         int i;
 107         for(i = 0; i < 1; i++) {
 108                 dump_spd_registers();
 109         }
 110 #endif
 111         disable_watchdogs();
 112         sdram_initialize(ARRAY_SIZE(mch), mch);
 113 #if 1
 114         dump_pci_device(PCI_DEV(0, 0x00, 0));
 115 //      dump_bar14(PCI_DEV(0, 0x00, 0));
 116 #endif
 117
 118 #if 0 // temporarily disabled
 119         /* Check the first 1M */
 120 //      ram_check(0x00000000, 0x000100000);
 121 //      ram_check(0x00000000, 0x000a0000);
 122         ram_check(0x00100000, 0x01000000);
 123         /* check the first 1M in the 3rd Gig */
 124         ram_check(0x30100000, 0x31000000);
 125 #endif
 126 #if 0
 127         ram_check(0x00000000, 0x02000000);
 128 #endif
 129
 130 #if 0
 131         while(1) {
 132                 hlt();
 133         }
 134 #endif
 135 }
 136