1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <arch/ioapic.h>
4 #include <device/pci.h>
8 static void *smp_write_config_table(void *v)
10 static const char sig[4] = "PCMP";
11 static const char oem[8] = "COREBOOT";
12 static const char productid[12] = "X6DAI-G ";
13 struct mp_config_table *mc;
14 unsigned char bus_num;
15 unsigned char bus_isa;
16 unsigned char bus_6300;
18 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
19 memset(mc, 0, sizeof(*mc));
21 memcpy(mc->mpc_signature, sig, sizeof(sig));
22 mc->mpc_length = sizeof(*mc); /* initially just the header */
24 mc->mpc_checksum = 0; /* not yet computed */
25 memcpy(mc->mpc_oem, oem, sizeof(oem));
26 memcpy(mc->mpc_productid, productid, sizeof(productid));
29 mc->mpc_entry_count = 0; /* No entries yet... */
30 mc->mpc_lapic = LAPIC_ADDR;
35 smp_write_processors(mc);
41 dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
43 bus_6300 = pci_read_config8(dev, PCI_SECONDARY_BUS);
44 bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
48 printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n");
54 /* define bus and isa numbers */
55 for(bus_num = 0; bus_num < bus_isa; bus_num++) {
56 smp_write_bus(mc, bus_num, "PCI ");
58 smp_write_bus(mc, bus_isa, "ISA ");
62 smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
63 smp_write_ioapic(mc, 3, 0x20, IO_APIC_ADDR + 0x10000);
65 mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0);
67 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
68 0x00, 0x74, 0x02, 0x10);
69 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
70 0x00, 0x77, 0x02, 0x17);
71 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
72 0x00, 0x75, 0x02, 0x13);
73 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
74 0x00, 0x7c, 0x02, 0x12);
75 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
76 0x00, 0x7d, 0x02, 0x11);
77 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
78 0x00, 0x7d, 0x02, 0x11);
79 /* Slot 1 function 0 */
80 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
82 /* Slot 2 function 0 */
83 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
85 /* Slot 3 function 0 */
86 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
87 bus_6300, 0x20, 0x02, 0x14);
88 /* Slot 4 function 0 */
89 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
90 bus_6300, 0x08, 0x02, 0x15);
92 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
93 bus_6300, 0x0c, 0x02, 0x16);
95 /* Standard local interrupt assignments */
96 // smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
97 // bus_isa, 0x00, MP_APIC_ALL, 0x00);
98 smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
99 bus_isa, 0x00, MP_APIC_ALL, 0x01);
101 /* There is no extension information... */
103 /* Compute the checksums */
104 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
106 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
107 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
108 mc, smp_next_mpe_entry(mc));
109 return smp_next_mpe_entry(mc);
112 unsigned long write_smp_table(unsigned long addr)
115 v = smp_write_floating_table(addr);
116 return (unsigned long)smp_write_config_table(v);