2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 AMD
5 * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 #define RAMINIT_SYSINFO 1
24 #define FAM10_SCAN_PCI_BUS 0
25 #define FAM10_ALLOCATE_IO_RANGE 1
27 #define QRANK_DIMM_SUPPORT 1
29 #if CONFIG_LOGICAL_CPUS==1
30 #define SET_NB_CFG_54 1
34 #define SET_FIDVID_CORE_RANGE 0
38 #include <device/pci_def.h>
39 #include <device/pci_ids.h>
41 #include <device/pnp_def.h>
42 #include <arch/romcc_io.h>
43 #include <cpu/x86/lapic.h>
44 #include "option_table.h"
45 #include "pc80/mc146818rtc_early.c"
48 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
50 #include "pc80/serial.c"
51 #include "console/console.c"
52 #include "lib/ramtest.c"
54 #include <cpu/amd/model_10xxx_rev.h>
56 //#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
57 #include "northbridge/amd/amdfam10/raminit.h"
58 #include "northbridge/amd/amdfam10/amdfam10.h"
60 #include "cpu/x86/lapic/boot_cpu.c"
61 #include "northbridge/amd/amdfam10/reset_test.c"
62 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
63 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
65 #include "cpu/x86/bist.h"
67 #include "northbridge/amd/amdfam10/debug.c"
69 #include "cpu/amd/mtrr/amd_earlymtrr.c"
71 #include "northbridge/amd/amdfam10/setup_resource_map.c"
73 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
75 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
77 static void memreset_setup(void)
81 static void memreset(int controllers, const struct mem_controller *ctrl)
85 static inline void activate_spd_rom(const struct mem_controller *ctrl)
87 #define SMBUS_SWITCH1 0x70
88 #define SMBUS_SWITCH2 0x72
89 smbus_send_byte(SMBUS_SWITCH1, 5 & 0x0f);
90 smbus_send_byte(SMBUS_SWITCH2, (5 >> 4) & 0x0f);
93 static inline int spd_read_byte(unsigned device, unsigned address)
95 return smbus_read_byte(device, address);
98 #include "northbridge/amd/amdfam10/amdfam10.h"
99 #include "northbridge/amd/amdht/ht_wrapper.c"
101 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
102 #include "northbridge/amd/amdfam10/raminit_amdmct.c"
103 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
105 #include "resourcemap.c"
107 #include "cpu/amd/quadcore/quadcore.c"
110 #define MCP55_USE_NIC 0
111 #define MCP55_USE_AZA 0
113 #define MCP55_PCI_E_X_0 4
115 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
116 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
118 #include "cpu/amd/car/copy_and_run.c"
120 #include "cpu/amd/car/post_cache_as_ram.c"
122 #include "cpu/amd/model_10xxx/init_cpus.c"
124 #include "cpu/amd/model_10xxx/fidvid.c"
126 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
127 #include "northbridge/amd/amdfam10/early_ht.c"
129 static void sio_setup(void)
136 // smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */
137 smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */
139 byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
141 pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
143 dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
145 pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
147 dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
149 pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
153 #include "spd_addr.h"
154 #include "cpu/amd/microcode/microcode.c"
155 #include "cpu/amd/model_10xxx/update_microcode.c"
157 #define GPIO1_DEV PNP_DEV(0x2e, W83627HF_GAME_MIDI_GPIO1)
158 #define GPIO2_DEV PNP_DEV(0x2e, W83627HF_GPIO2)
159 #define GPIO3_DEV PNP_DEV(0x2e, W83627HF_GPIO3)
160 void write_GPIO(void)
162 pnp_enter_ext_func_mode(GPIO1_DEV);
163 pnp_set_logical_device(GPIO1_DEV);
164 pnp_write_config(GPIO1_DEV, 0x30, 0x01);
165 pnp_write_config(GPIO1_DEV, 0x60, 0x00);
166 pnp_write_config(GPIO1_DEV, 0x61, 0x00);
167 pnp_write_config(GPIO1_DEV, 0x62, 0x00);
168 pnp_write_config(GPIO1_DEV, 0x63, 0x00);
169 pnp_write_config(GPIO1_DEV, 0x70, 0x00);
170 pnp_write_config(GPIO1_DEV, 0xf0, 0xff);
171 pnp_write_config(GPIO1_DEV, 0xf1, 0xff);
172 pnp_write_config(GPIO1_DEV, 0xf2, 0x00);
173 pnp_exit_ext_func_mode(GPIO1_DEV);
175 pnp_enter_ext_func_mode(GPIO2_DEV);
176 pnp_set_logical_device(GPIO2_DEV);
177 pnp_write_config(GPIO2_DEV, 0x30, 0x01);
178 pnp_write_config(GPIO2_DEV, 0xf0, 0xef);
179 pnp_write_config(GPIO2_DEV, 0xf1, 0xff);
180 pnp_write_config(GPIO2_DEV, 0xf2, 0x00);
181 pnp_write_config(GPIO2_DEV, 0xf3, 0x00);
182 pnp_write_config(GPIO2_DEV, 0xf5, 0x48);
183 pnp_write_config(GPIO2_DEV, 0xf6, 0x00);
184 pnp_write_config(GPIO2_DEV, 0xf7, 0xc0);
185 pnp_exit_ext_func_mode(GPIO2_DEV);
187 pnp_enter_ext_func_mode(GPIO3_DEV);
188 pnp_set_logical_device(GPIO3_DEV);
189 pnp_write_config(GPIO3_DEV, 0x30, 0x00);
190 pnp_write_config(GPIO3_DEV, 0xf0, 0xff);
191 pnp_write_config(GPIO3_DEV, 0xf1, 0xff);
192 pnp_write_config(GPIO3_DEV, 0xf2, 0xff);
193 pnp_write_config(GPIO3_DEV, 0xf3, 0x40);
194 pnp_exit_ext_func_mode(GPIO3_DEV);
197 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
199 struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
206 if (!cpu_init_detectedx && boot_cpu()) {
207 /* Nothing special needs to be done to find bus 0 */
208 /* Allow the HT devices to be found */
210 set_bsp_node_CHtExtNodeCfgEn();
211 enumerate_ht_chain();
215 /* Setup the mcp55 */
222 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
227 pnp_enter_ext_func_mode(SERIAL_DEV);
228 pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6));
229 w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
230 pnp_exit_ext_func_mode(SERIAL_DEV);
235 printk(BIOS_DEBUG, "\n");
237 /* Halt if there was a built in self test failure */
238 report_bist_failure(bist);
241 printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
242 printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
243 printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
244 printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
246 /* Setup sysinfo defaults */
247 set_sysinfo_in_ram(0);
249 update_microcode(val);
255 amd_ht_init(sysinfo);
258 /* Setup nodes PCI space and start core 0 AP init. */
259 finalize_node_setup(sysinfo);
261 /* Setup any mainboard PCI settings etc. */
262 setup_mb_resource_map();
265 /* wait for all the APs core0 started by finalize_node_setup. */
266 /* FIXME: A bunch of cores are going to start output to serial at once.
267 * It would be nice to fixup prink spinlocks for ROM XIP mode.
268 * I think it could be done by putting the spinlock flag in the cache
269 * of the BSP located right after sysinfo.
272 wait_all_core0_started();
273 #if CONFIG_LOGICAL_CPUS==1
274 /* Core0 on each node is configured. Now setup any additional cores. */
275 printk(BIOS_DEBUG, "start_other_cores()\n");
278 wait_all_other_cores_started(bsp_apicid);
284 msr = rdmsr(0xc0010071);
285 printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
287 /* FIXME: The sb fid change may survive the warm reset and only
288 * need to be done once.*/
290 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
293 if (!warm_reset_detect(0)) { // BSP is node 0
294 init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
296 init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
301 /* show final fid and vid */
302 msr=rdmsr(0xc0010071);
303 printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
306 wants_reset = mcp55_early_setup_x();
308 /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
309 if (!warm_reset_detect(0)) {
310 print_info("...WARM RESET...\n\n\n");
312 die("After soft_reset_x - shouldn't see this message!!!\n");
316 printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n");
320 /* It's the time to set ctrl in sysinfo now; */
321 printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
322 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
326 //printk(BIOS_DEBUG, "enable_smbus()\n");
327 // enable_smbus(); /* enable in sio_setup */
335 printk(BIOS_DEBUG, "raminit_amdmct()\n");
336 raminit_amdmct(sysinfo);
339 // printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
340 post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
341 post_code(0x42); // Should never see this post code.