src/mainboard/supermicro/h8qme_fam10/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 AMD
   5  * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  20  */
  21
  22 #define ASSEMBLY 1
  23 #define __PRE_RAM__
  24
  25 #define RAMINIT_SYSINFO 1
  26
  27 #define FAM10_SCAN_PCI_BUS 0
  28 #define FAM10_ALLOCATE_IO_RANGE 1
  29
  30 #define QRANK_DIMM_SUPPORT 1
  31
  32 #if CONFIG_LOGICAL_CPUS==1
  33 #define SET_NB_CFG_54 1
  34 #endif
  35
  36 #define FAM10_SET_FIDVID 1
  37 #define FAM10_SET_FIDVID_CORE_RANGE 0
  38
  39 #include <stdint.h>
  40 #include <string.h>
  41 #include <device/pci_def.h>
  42 #include <device/pci_ids.h>
  43 #include <arch/io.h>
  44 #include <device/pnp_def.h>
  45 #include <arch/romcc_io.h>
  46 #include <cpu/x86/lapic.h>
  47 #include "option_table.h"
  48 #include "pc80/mc146818rtc_early.c"
  49
  50 // for enable the FAN
  51 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
  52
  53 #include "pc80/serial.c"
  54 #include "arch/i386/lib/console.c"
  55 #include "lib/ramtest.c"
  56
  57 #include <cpu/amd/model_10xxx_rev.h>
  58
  59 //#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
  60 #include "northbridge/amd/amdfam10/raminit.h"
  61 #include "northbridge/amd/amdfam10/amdfam10.h"
  62
  63 #include "cpu/x86/lapic/boot_cpu.c"
  64 #include "northbridge/amd/amdfam10/reset_test.c"
  65 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  66 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
  67
  68 #include "cpu/x86/bist.h"
  69
  70 #include "northbridge/amd/amdfam10/debug.c"
  71
  72 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  73
  74
  75 #include "northbridge/amd/amdfam10/setup_resource_map.c"
  76
  77 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  78
  79 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
  80
  81 static void memreset_setup(void)
  82 {
  83 }
  84
  85 static void memreset(int controllers, const struct mem_controller *ctrl)
  86 {
  87 }
  88
  89 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  90 {
  91 #define SMBUS_SWITCH1 0x70
  92 #define SMBUS_SWITCH2 0x72
  93         smbus_send_byte(SMBUS_SWITCH1, 5 & 0x0f);
  94         smbus_send_byte(SMBUS_SWITCH2, (5 >> 4) & 0x0f);
  95 }
  96
  97 static inline int spd_read_byte(unsigned device, unsigned address)
  98 {
  99         return smbus_read_byte(device, address);
 100 }
 101
 102 #include "northbridge/amd/amdfam10/amdfam10.h"
 103 #include "northbridge/amd/amdht/ht_wrapper.c"
 104
 105 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
 106 #include "northbridge/amd/amdfam10/raminit_amdmct.c"
 107 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
 108
 109 #include "resourcemap.c"
 110
 111 #include "cpu/amd/quadcore/quadcore.c"
 112
 113 #define MCP55_NUM 1
 114 #define MCP55_USE_NIC 0
 115 #define MCP55_USE_AZA 0
 116
 117 #define MCP55_PCI_E_X_0 4
 118
 119 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 120 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
 121
 122 #include "cpu/amd/car/copy_and_run.c"
 123
 124 #include "cpu/amd/car/post_cache_as_ram.c"
 125
 126 #include "cpu/amd/model_10xxx/init_cpus.c"
 127
 128 #include "cpu/amd/model_10xxx/fidvid.c"
 129
 130 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 131 #include "northbridge/amd/amdfam10/early_ht.c"
 132
 133
 134 static void sio_setup(void)
 135 {
 136
 137         unsigned value;
 138         uint32_t dword;
 139         uint8_t byte;
 140         enable_smbus();
 141 //      smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */
 142         smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */
 143
 144         byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
 145         byte |= 0x20;
 146         pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
 147
 148         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
 149         dword |= (1<<0);
 150         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
 151
 152         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
 153         dword |= (1<<16);
 154         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
 155
 156 }
 157
 158 #include "spd_addr.h"
 159 #include "cpu/amd/microcode/microcode.c"
 160 #include "cpu/amd/model_10xxx/update_microcode.c"
 161
 162 #define GPIO1_DEV PNP_DEV(0x2e, W83627HF_GAME_MIDI_GPIO1)
 163 #define GPIO2_DEV PNP_DEV(0x2e, W83627HF_GPIO2)
 164 #define GPIO3_DEV PNP_DEV(0x2e, W83627HF_GPIO3)
 165 void write_GPIO(void)
 166 {
 167         pnp_enter_ext_func_mode(GPIO1_DEV);
 168         pnp_set_logical_device(GPIO1_DEV);
 169         pnp_write_config(GPIO1_DEV, 0x30, 0x01);
 170         pnp_write_config(GPIO1_DEV, 0x60, 0x00);
 171         pnp_write_config(GPIO1_DEV, 0x61, 0x00);
 172         pnp_write_config(GPIO1_DEV, 0x62, 0x00);
 173         pnp_write_config(GPIO1_DEV, 0x63, 0x00);
 174         pnp_write_config(GPIO1_DEV, 0x70, 0x00);
 175         pnp_write_config(GPIO1_DEV, 0xf0, 0xff);
 176         pnp_write_config(GPIO1_DEV, 0xf1, 0xff);
 177         pnp_write_config(GPIO1_DEV, 0xf2, 0x00);
 178         pnp_exit_ext_func_mode(GPIO1_DEV);
 179
 180         pnp_enter_ext_func_mode(GPIO2_DEV);
 181         pnp_set_logical_device(GPIO2_DEV);
 182         pnp_write_config(GPIO2_DEV, 0x30, 0x01);
 183         pnp_write_config(GPIO2_DEV, 0xf0, 0xef);
 184         pnp_write_config(GPIO2_DEV, 0xf1, 0xff);
 185         pnp_write_config(GPIO2_DEV, 0xf2, 0x00);
 186         pnp_write_config(GPIO2_DEV, 0xf3, 0x00);
 187         pnp_write_config(GPIO2_DEV, 0xf5, 0x48);
 188         pnp_write_config(GPIO2_DEV, 0xf6, 0x00);
 189         pnp_write_config(GPIO2_DEV, 0xf7, 0xc0);
 190         pnp_exit_ext_func_mode(GPIO2_DEV);
 191
 192         pnp_enter_ext_func_mode(GPIO3_DEV);
 193         pnp_set_logical_device(GPIO3_DEV);
 194         pnp_write_config(GPIO3_DEV, 0x30, 0x00);
 195         pnp_write_config(GPIO3_DEV, 0xf0, 0xff);
 196         pnp_write_config(GPIO3_DEV, 0xf1, 0xff);
 197         pnp_write_config(GPIO3_DEV, 0xf2, 0xff);
 198         pnp_write_config(GPIO3_DEV, 0xf3, 0x40);
 199         pnp_exit_ext_func_mode(GPIO3_DEV);
 200 }
 201
 202 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 203 {
 204   struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 205
 206         u32 bsp_apicid = 0;
 207         u32 val;
 208         u32 wants_reset;
 209         msr_t msr;
 210
 211         if (!cpu_init_detectedx && boot_cpu()) {
 212                 /* Nothing special needs to be done to find bus 0 */
 213                 /* Allow the HT devices to be found */
 214
 215                 set_bsp_node_CHtExtNodeCfgEn();
 216                 enumerate_ht_chain();
 217
 218                 sio_setup();
 219
 220                 /* Setup the mcp55 */
 221                 mcp55_enable_rom();
 222         }
 223
 224   post_code(0x30);
 225
 226         if (bist == 0) {
 227                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 228         }
 229
 230   post_code(0x32);
 231
 232         pnp_enter_ext_func_mode(SERIAL_DEV);
 233         pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6));
 234         w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
 235         pnp_exit_ext_func_mode(SERIAL_DEV);
 236
 237         uart_init();
 238         console_init();
 239         write_GPIO();
 240         printk(BIOS_DEBUG, "\n");
 241
 242         /* Halt if there was a built in self test failure */
 243         report_bist_failure(bist);
 244
 245  val = cpuid_eax(1);
 246  printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
 247  printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 248  printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
 249  printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
 250
 251  /* Setup sysinfo defaults */
 252  set_sysinfo_in_ram(0);
 253
 254  update_microcode(val);
 255  post_code(0x33);
 256
 257  cpuSetAMDMSR();
 258  post_code(0x34);
 259
 260  amd_ht_init(sysinfo);
 261  post_code(0x35);
 262
 263  /* Setup nodes PCI space and start core 0 AP init. */
 264  finalize_node_setup(sysinfo);
 265
 266  /* Setup any mainboard PCI settings etc. */
 267  setup_mb_resource_map();
 268  post_code(0x36);
 269
 270  /* wait for all the APs core0 started by finalize_node_setup. */
 271  /* FIXME: A bunch of cores are going to start output to serial at once.
 272   * It would be nice to fixup prink spinlocks for ROM XIP mode.
 273   * I think it could be done by putting the spinlock flag in the cache
 274   * of the BSP located right after sysinfo.
 275   */
 276
 277         wait_all_core0_started();
 278 #if CONFIG_LOGICAL_CPUS==1
 279  /* Core0 on each node is configured. Now setup any additional cores. */
 280  printk(BIOS_DEBUG, "start_other_cores()\n");
 281         start_other_cores();
 282  post_code(0x37);
 283         wait_all_other_cores_started(bsp_apicid);
 284 #endif
 285
 286  post_code(0x38);
 287
 288 #if FAM10_SET_FIDVID == 1
 289  msr = rdmsr(0xc0010071);
 290  printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 291
 292  /* FIXME: The sb fid change may survive the warm reset and only
 293   * need to be done once.*/
 294
 295         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 296  post_code(0x39);
 297
 298  if (!warm_reset_detect(0)) {      // BSP is node 0
 299    init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
 300  } else {
 301    init_fidvid_stage2(bsp_apicid, 0);  // BSP is node 0
 302         }
 303
 304  post_code(0x3A);
 305
 306  /* show final fid and vid */
 307  msr=rdmsr(0xc0010071);
 308  printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 309 #endif
 310
 311  wants_reset = mcp55_early_setup_x();
 312
 313  /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
 314  if (!warm_reset_detect(0)) {
 315    print_info("...WARM RESET...\n\n\n");
 316                 soft_reset();
 317    die("After soft_reset_x - shouldn't see this message!!!\n");
 318         }
 319
 320  if (wants_reset)
 321    printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n");
 322
 323  post_code(0x3B);
 324
 325 /* It's the time to set ctrl in sysinfo now; */
 326 printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
 327 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 328
 329 post_code(0x3D);
 330
 331 //printk(BIOS_DEBUG, "enable_smbus()\n");
 332 //        enable_smbus(); /* enable in sio_setup */
 333
 334 post_code(0x3E);
 335
 336         memreset_setup();
 337
 338 post_code(0x40);
 339
 340
 341  printk(BIOS_DEBUG, "raminit_amdmct()\n");
 342  raminit_amdmct(sysinfo);
 343  post_code(0x41);
 344
 345 // printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
 346  post_cache_as_ram();  // BSP switch stack to ram, copy then execute LB.
 347  post_code(0x42);  // Should never see this post code.
 348
 349 }
 350