src/mainboard/supermicro/h8qme_fam10/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 AMD
   5  * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  20  */
  21
  22 #define ASSEMBLY 1
  23 #define __PRE_RAM__
  24
  25 #define RAMINIT_SYSINFO 1
  26
  27 #define FAM10_SCAN_PCI_BUS 0
  28 #define FAM10_ALLOCATE_IO_RANGE 1
  29
  30 #define QRANK_DIMM_SUPPORT 1
  31
  32 #if CONFIG_LOGICAL_CPUS==1
  33 #define SET_NB_CFG_54 1
  34 #endif
  35
  36 #define FAM10_SET_FIDVID 1
  37 #define FAM10_SET_FIDVID_CORE_RANGE 0
  38
  39 #include <stdint.h>
  40 #include <string.h>
  41 #include <device/pci_def.h>
  42 #include <device/pci_ids.h>
  43 #include <arch/io.h>
  44 #include <device/pnp_def.h>
  45 #include <arch/romcc_io.h>
  46 #include <cpu/x86/lapic.h>
  47 #include "option_table.h"
  48 #include "pc80/mc146818rtc_early.c"
  49
  50 // for enable the FAN
  51 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
  52
  53 static void post_code(u8 value) {
  54         outb(value, 0x80);
  55 }
  56
  57 #if CONFIG_USE_FAILOVER_IMAGE==0
  58 #include "pc80/serial.c"
  59 #include "arch/i386/lib/console.c"
  60 #include "lib/ramtest.c"
  61
  62 #include <cpu/amd/model_10xxx_rev.h>
  63
  64 //#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
  65 #include "northbridge/amd/amdfam10/raminit.h"
  66 #include "northbridge/amd/amdfam10/amdfam10.h"
  67
  68 #endif
  69
  70 #include "cpu/x86/lapic/boot_cpu.c"
  71 #include "northbridge/amd/amdfam10/reset_test.c"
  72 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  73 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
  74
  75 #if CONFIG_USE_FAILOVER_IMAGE==0
  76
  77 #include "cpu/x86/bist.h"
  78
  79 #include "northbridge/amd/amdfam10/debug.c"
  80
  81 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  82
  83
  84 #include "northbridge/amd/amdfam10/setup_resource_map.c"
  85
  86 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  87
  88 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
  89
  90 static void memreset_setup(void)
  91 {
  92 }
  93
  94 static void memreset(int controllers, const struct mem_controller *ctrl)
  95 {
  96 }
  97
  98 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  99 {
 100 #define SMBUS_SWITCH1 0x70
 101 #define SMBUS_SWITCH2 0x72
 102         smbus_send_byte(SMBUS_SWITCH1, 5 & 0x0f);
 103         smbus_send_byte(SMBUS_SWITCH2, (5 >> 4) & 0x0f);
 104 }
 105
 106 static inline int spd_read_byte(unsigned device, unsigned address)
 107 {
 108         return smbus_read_byte(device, address);
 109 }
 110
 111 #include "northbridge/amd/amdfam10/amdfam10.h"
 112 #include "northbridge/amd/amdht/ht_wrapper.c"
 113
 114 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
 115 #include "northbridge/amd/amdfam10/raminit_amdmct.c"
 116 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
 117
 118 #include "resourcemap.c"
 119
 120 #include "cpu/amd/quadcore/quadcore.c"
 121
 122 #define MCP55_NUM 1
 123 #define MCP55_USE_NIC 0
 124 #define MCP55_USE_AZA 0
 125
 126 #define MCP55_PCI_E_X_0 4
 127
 128 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 129 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
 130
 131 #include "cpu/amd/car/copy_and_run.c"
 132
 133 #include "cpu/amd/car/post_cache_as_ram.c"
 134
 135 #include "cpu/amd/model_10xxx/init_cpus.c"
 136
 137 #include "cpu/amd/model_10xxx/fidvid.c"
 138
 139 #endif
 140
 141 #if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
 142
 143 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 144 #include "northbridge/amd/amdfam10/early_ht.c"
 145
 146
 147 static void sio_setup(void)
 148 {
 149
 150         unsigned value;
 151         uint32_t dword;
 152         uint8_t byte;
 153         enable_smbus();
 154 //      smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */
 155         smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */
 156
 157         byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
 158         byte |= 0x20;
 159         pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
 160
 161         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
 162         dword |= (1<<0);
 163         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
 164
 165         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
 166         dword |= (1<<16);
 167         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
 168
 169 }
 170
 171 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 172 {
 173         unsigned last_boot_normal_x = last_boot_normal();
 174
 175         /* Is this a cpu only reset? or Is this a secondary cpu? */
 176         if ((cpu_init_detectedx) || (!boot_cpu())) {
 177                 if (last_boot_normal_x) {
 178                         goto normal_image;
 179                 } else {
 180                         goto fallback_image;
 181                 }
 182         }
 183
 184         /* Nothing special needs to be done to find bus 0 */
 185         /* Allow the HT devices to be found */
 186
 187         set_bsp_node_CHtExtNodeCfgEn();
 188         enumerate_ht_chain();
 189
 190         sio_setup();
 191
 192         /* Setup the mcp55 */
 193         mcp55_enable_rom();
 194
 195         /* Is this a deliberate reset by the bios */
 196         if (bios_reset_detected() && last_boot_normal_x) {
 197                 goto normal_image;
 198         }
 199         /* This is the primary cpu how should I boot? */
 200         else if (do_normal_boot()) {
 201                 goto normal_image;
 202         }
 203         else {
 204                 goto fallback_image;
 205         }
 206  normal_image:
 207         __asm__ volatile ("jmp __normal_image"
 208                 : /* outputs */
 209                 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
 210                 );
 211
 212  fallback_image:
 213 #if CONFIG_HAVE_FAILOVER_BOOT==1
 214         __asm__ volatile ("jmp __fallback_image"
 215                 : /* outputs */
 216                 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
 217                 )
 218 #endif
 219         ;
 220 }
 221 #endif
 222 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 223
 224 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 225 {
 226 #if CONFIG_HAVE_FAILOVER_BOOT==1
 227     #if CONFIG_USE_FAILOVER_IMAGE==1
 228         failover_process(bist, cpu_init_detectedx);
 229     #else
 230         real_main(bist, cpu_init_detectedx);
 231     #endif
 232 #else
 233     #if CONFIG_USE_FALLBACK_IMAGE == 1
 234         failover_process(bist, cpu_init_detectedx);
 235     #endif
 236         real_main(bist, cpu_init_detectedx);
 237 #endif
 238 }
 239
 240 #if CONFIG_USE_FAILOVER_IMAGE==0
 241 #include "spd_addr.h"
 242 #include "cpu/amd/microcode/microcode.c"
 243 #include "cpu/amd/model_10xxx/update_microcode.c"
 244
 245 #define GPIO1_DEV PNP_DEV(0x2e, W83627HF_GAME_MIDI_GPIO1)
 246 #define GPIO2_DEV PNP_DEV(0x2e, W83627HF_GPIO2)
 247 #define GPIO3_DEV PNP_DEV(0x2e, W83627HF_GPIO3)
 248 void write_GPIO(void)
 249 {
 250         pnp_enter_ext_func_mode(GPIO1_DEV);
 251         pnp_set_logical_device(GPIO1_DEV);
 252         pnp_write_config(GPIO1_DEV, 0x30, 0x01);
 253         pnp_write_config(GPIO1_DEV, 0x60, 0x00);
 254         pnp_write_config(GPIO1_DEV, 0x61, 0x00);
 255         pnp_write_config(GPIO1_DEV, 0x62, 0x00);
 256         pnp_write_config(GPIO1_DEV, 0x63, 0x00);
 257         pnp_write_config(GPIO1_DEV, 0x70, 0x00);
 258         pnp_write_config(GPIO1_DEV, 0xf0, 0xff);
 259         pnp_write_config(GPIO1_DEV, 0xf1, 0xff);
 260         pnp_write_config(GPIO1_DEV, 0xf2, 0x00);
 261         pnp_exit_ext_func_mode(GPIO1_DEV);
 262
 263         pnp_enter_ext_func_mode(GPIO2_DEV);
 264         pnp_set_logical_device(GPIO2_DEV);
 265         pnp_write_config(GPIO2_DEV, 0x30, 0x01);
 266         pnp_write_config(GPIO2_DEV, 0xf0, 0xef);
 267         pnp_write_config(GPIO2_DEV, 0xf1, 0xff);
 268         pnp_write_config(GPIO2_DEV, 0xf2, 0x00);
 269         pnp_write_config(GPIO2_DEV, 0xf3, 0x00);
 270         pnp_write_config(GPIO2_DEV, 0xf5, 0x48);
 271         pnp_write_config(GPIO2_DEV, 0xf6, 0x00);
 272         pnp_write_config(GPIO2_DEV, 0xf7, 0xc0);
 273         pnp_exit_ext_func_mode(GPIO2_DEV);
 274
 275         pnp_enter_ext_func_mode(GPIO3_DEV);
 276         pnp_set_logical_device(GPIO3_DEV);
 277         pnp_write_config(GPIO3_DEV, 0x30, 0x00);
 278         pnp_write_config(GPIO3_DEV, 0xf0, 0xff);
 279         pnp_write_config(GPIO3_DEV, 0xf1, 0xff);
 280         pnp_write_config(GPIO3_DEV, 0xf2, 0xff);
 281         pnp_write_config(GPIO3_DEV, 0xf3, 0x40);
 282         pnp_exit_ext_func_mode(GPIO3_DEV);
 283 }
 284
 285 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 286 {
 287   struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 288
 289         u32 bsp_apicid = 0;
 290         u32 val;
 291         u32 wants_reset;
 292         msr_t msr;
 293
 294   post_code(0x30);
 295
 296         if (bist == 0) {
 297                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 298         }
 299
 300   post_code(0x32);
 301
 302         pnp_enter_ext_func_mode(SERIAL_DEV);
 303         pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6));
 304         w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
 305         pnp_exit_ext_func_mode(SERIAL_DEV);
 306
 307         uart_init();
 308         console_init();
 309         write_GPIO();
 310         printk_debug("\n");
 311
 312         /* Halt if there was a built in self test failure */
 313         report_bist_failure(bist);
 314
 315  val = cpuid_eax(1);
 316  printk_debug("BSP Family_Model: %08x \n", val);
 317  printk_debug("*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n");
 318  printk_debug("bsp_apicid = %02x \n", bsp_apicid);
 319  printk_debug("cpu_init_detectedx = %08x \n", cpu_init_detectedx);
 320
 321  /* Setup sysinfo defaults */
 322  set_sysinfo_in_ram(0);
 323
 324  update_microcode(val);
 325  post_code(0x33);
 326
 327  cpuSetAMDMSR();
 328  post_code(0x34);
 329
 330  amd_ht_init(sysinfo);
 331  post_code(0x35);
 332
 333  /* Setup nodes PCI space and start core 0 AP init. */
 334  finalize_node_setup(sysinfo);
 335
 336  /* Setup any mainboard PCI settings etc. */
 337  setup_mb_resource_map();
 338  post_code(0x36);
 339
 340  /* wait for all the APs core0 started by finalize_node_setup. */
 341  /* FIXME: A bunch of cores are going to start output to serial at once.
 342   * It would be nice to fixup prink spinlocks for ROM XIP mode.
 343   * I think it could be done by putting the spinlock flag in the cache
 344   * of the BSP located right after sysinfo.
 345   */
 346
 347         wait_all_core0_started();
 348 #if CONFIG_LOGICAL_CPUS==1
 349  /* Core0 on each node is configured. Now setup any additional cores. */
 350  printk_debug("start_other_cores()\n");
 351         start_other_cores();
 352  post_code(0x37);
 353         wait_all_other_cores_started(bsp_apicid);
 354 #endif
 355
 356  post_code(0x38);
 357
 358 #if FAM10_SET_FIDVID == 1
 359  msr = rdmsr(0xc0010071);
 360  printk_debug("\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 361
 362  /* FIXME: The sb fid change may survive the warm reset and only
 363   * need to be done once.*/
 364
 365         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 366  post_code(0x39);
 367
 368  if (!warm_reset_detect(0)) {      // BSP is node 0
 369    init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
 370  } else {
 371    init_fidvid_stage2(bsp_apicid, 0);  // BSP is node 0
 372         }
 373
 374  post_code(0x3A);
 375
 376  /* show final fid and vid */
 377  msr=rdmsr(0xc0010071);
 378  printk_debug("End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 379 #endif
 380
 381  wants_reset = mcp55_early_setup_x();
 382
 383  /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
 384  if (!warm_reset_detect(0)) {
 385    print_info("...WARM RESET...\n\n\n");
 386                 soft_reset();
 387    die("After soft_reset_x - shouldn't see this message!!!\n");
 388         }
 389
 390  if (wants_reset)
 391    printk_debug("mcp55_early_setup_x wanted additional reset!\n");
 392
 393  post_code(0x3B);
 394
 395 /* It's the time to set ctrl in sysinfo now; */
 396 printk_debug("fill_mem_ctrl()\n");
 397 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 398
 399 post_code(0x3D);
 400
 401 //printk_debug("enable_smbus()\n");
 402 //        enable_smbus(); /* enable in sio_setup */
 403
 404 post_code(0x3E);
 405
 406         memreset_setup();
 407
 408 post_code(0x40);
 409
 410
 411  printk_debug("raminit_amdmct()\n");
 412  raminit_amdmct(sysinfo);
 413  post_code(0x41);
 414
 415 // printk_debug("\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
 416  post_cache_as_ram();  // BSP switch stack to ram, copy then execute LB.
 417  post_code(0x42);  // Should never see this post code.
 418
 419 }
 420
 421
 422 #endif