src/mainboard/supermicro/h8qme_fam10/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 AMD
   5  * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  20  */
  21
  22 #define RAMINIT_SYSINFO 1
  23
  24 #define FAM10_SCAN_PCI_BUS 0
  25 #define FAM10_ALLOCATE_IO_RANGE 1
  26
  27 #define QRANK_DIMM_SUPPORT 1
  28
  29 #if CONFIG_LOGICAL_CPUS==1
  30 #define SET_NB_CFG_54 1
  31 #endif
  32
  33 #define SET_FIDVID 1
  34 #define SET_FIDVID_CORE_RANGE 0
  35
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <device/pci_def.h>
  39 #include <device/pci_ids.h>
  40 #include <arch/io.h>
  41 #include <device/pnp_def.h>
  42 #include <arch/romcc_io.h>
  43 #include <cpu/x86/lapic.h>
  44 #include "option_table.h"
  45 #include "pc80/mc146818rtc_early.c"
  46
  47 // for enable the FAN
  48 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
  49
  50 #include "pc80/serial.c"
  51 #include "console/console.c"
  52 #include "lib/ramtest.c"
  53
  54 #include <cpu/amd/model_10xxx_rev.h>
  55
  56 //#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
  57 #include "northbridge/amd/amdfam10/raminit.h"
  58 #include "northbridge/amd/amdfam10/amdfam10.h"
  59
  60 #include "cpu/x86/lapic/boot_cpu.c"
  61 #include "northbridge/amd/amdfam10/reset_test.c"
  62 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  63 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
  64
  65 #include "cpu/x86/bist.h"
  66
  67 #include "northbridge/amd/amdfam10/debug.c"
  68
  69 #include "cpu/x86/mtrr/earlymtrr.c"
  70
  71 #include "northbridge/amd/amdfam10/setup_resource_map.c"
  72
  73 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  74
  75 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
  76
  77 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  78 {
  79 #define SMBUS_SWITCH1 0x70
  80 #define SMBUS_SWITCH2 0x72
  81         smbus_send_byte(SMBUS_SWITCH1, 5 & 0x0f);
  82         smbus_send_byte(SMBUS_SWITCH2, (5 >> 4) & 0x0f);
  83 }
  84
  85 static inline int spd_read_byte(unsigned device, unsigned address)
  86 {
  87         return smbus_read_byte(device, address);
  88 }
  89
  90 #include "northbridge/amd/amdfam10/amdfam10.h"
  91 #include "northbridge/amd/amdht/ht_wrapper.c"
  92
  93 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
  94 #include "northbridge/amd/amdfam10/raminit_amdmct.c"
  95 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
  96
  97 #include "resourcemap.c"
  98
  99 #include "cpu/amd/quadcore/quadcore.c"
 100
 101 #define MCP55_NUM 1
 102 #define MCP55_USE_NIC 0
 103 #define MCP55_USE_AZA 0
 104
 105 #define MCP55_PCI_E_X_0 4
 106
 107 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 108 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
 109
 110
 111
 112 #include "cpu/amd/car/post_cache_as_ram.c"
 113
 114 #include "cpu/amd/model_10xxx/init_cpus.c"
 115
 116 #include "cpu/amd/model_10xxx/fidvid.c"
 117
 118 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 119 #include "northbridge/amd/amdfam10/early_ht.c"
 120
 121 static void sio_setup(void)
 122 {
 123
 124         unsigned value;
 125         uint32_t dword;
 126         uint8_t byte;
 127         enable_smbus();
 128 //      smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */
 129         smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */
 130
 131         byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
 132         byte |= 0x20;
 133         pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
 134
 135         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
 136         dword |= (1<<0);
 137         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
 138
 139         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
 140         dword |= (1<<16);
 141         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
 142
 143 }
 144
 145 #include "spd_addr.h"
 146 #include "cpu/amd/microcode/microcode.c"
 147 #include "cpu/amd/model_10xxx/update_microcode.c"
 148
 149 #define GPIO1_DEV PNP_DEV(0x2e, W83627HF_GAME_MIDI_GPIO1)
 150 #define GPIO2_DEV PNP_DEV(0x2e, W83627HF_GPIO2)
 151 #define GPIO3_DEV PNP_DEV(0x2e, W83627HF_GPIO3)
 152 void write_GPIO(void)
 153 {
 154         pnp_enter_ext_func_mode(GPIO1_DEV);
 155         pnp_set_logical_device(GPIO1_DEV);
 156         pnp_write_config(GPIO1_DEV, 0x30, 0x01);
 157         pnp_write_config(GPIO1_DEV, 0x60, 0x00);
 158         pnp_write_config(GPIO1_DEV, 0x61, 0x00);
 159         pnp_write_config(GPIO1_DEV, 0x62, 0x00);
 160         pnp_write_config(GPIO1_DEV, 0x63, 0x00);
 161         pnp_write_config(GPIO1_DEV, 0x70, 0x00);
 162         pnp_write_config(GPIO1_DEV, 0xf0, 0xff);
 163         pnp_write_config(GPIO1_DEV, 0xf1, 0xff);
 164         pnp_write_config(GPIO1_DEV, 0xf2, 0x00);
 165         pnp_exit_ext_func_mode(GPIO1_DEV);
 166
 167         pnp_enter_ext_func_mode(GPIO2_DEV);
 168         pnp_set_logical_device(GPIO2_DEV);
 169         pnp_write_config(GPIO2_DEV, 0x30, 0x01);
 170         pnp_write_config(GPIO2_DEV, 0xf0, 0xef);
 171         pnp_write_config(GPIO2_DEV, 0xf1, 0xff);
 172         pnp_write_config(GPIO2_DEV, 0xf2, 0x00);
 173         pnp_write_config(GPIO2_DEV, 0xf3, 0x00);
 174         pnp_write_config(GPIO2_DEV, 0xf5, 0x48);
 175         pnp_write_config(GPIO2_DEV, 0xf6, 0x00);
 176         pnp_write_config(GPIO2_DEV, 0xf7, 0xc0);
 177         pnp_exit_ext_func_mode(GPIO2_DEV);
 178
 179         pnp_enter_ext_func_mode(GPIO3_DEV);
 180         pnp_set_logical_device(GPIO3_DEV);
 181         pnp_write_config(GPIO3_DEV, 0x30, 0x00);
 182         pnp_write_config(GPIO3_DEV, 0xf0, 0xff);
 183         pnp_write_config(GPIO3_DEV, 0xf1, 0xff);
 184         pnp_write_config(GPIO3_DEV, 0xf2, 0xff);
 185         pnp_write_config(GPIO3_DEV, 0xf3, 0x40);
 186         pnp_exit_ext_func_mode(GPIO3_DEV);
 187 }
 188
 189 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 190 {
 191   struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 192
 193         u32 bsp_apicid = 0;
 194         u32 val;
 195         u32 wants_reset;
 196         msr_t msr;
 197
 198         if (!cpu_init_detectedx && boot_cpu()) {
 199                 /* Nothing special needs to be done to find bus 0 */
 200                 /* Allow the HT devices to be found */
 201
 202                 set_bsp_node_CHtExtNodeCfgEn();
 203                 enumerate_ht_chain();
 204
 205                 sio_setup();
 206
 207                 /* Setup the mcp55 */
 208                 mcp55_enable_rom();
 209         }
 210
 211   post_code(0x30);
 212
 213         if (bist == 0) {
 214                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 215         }
 216
 217   post_code(0x32);
 218
 219         pnp_enter_ext_func_mode(SERIAL_DEV);
 220         pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6));
 221         w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
 222         pnp_exit_ext_func_mode(SERIAL_DEV);
 223
 224         uart_init();
 225         console_init();
 226         write_GPIO();
 227         printk(BIOS_DEBUG, "\n");
 228
 229         /* Halt if there was a built in self test failure */
 230         report_bist_failure(bist);
 231
 232  val = cpuid_eax(1);
 233  printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
 234  printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 235  printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
 236  printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
 237
 238  /* Setup sysinfo defaults */
 239  set_sysinfo_in_ram(0);
 240
 241  update_microcode(val);
 242  post_code(0x33);
 243
 244  cpuSetAMDMSR();
 245  post_code(0x34);
 246
 247  amd_ht_init(sysinfo);
 248  post_code(0x35);
 249
 250  /* Setup nodes PCI space and start core 0 AP init. */
 251  finalize_node_setup(sysinfo);
 252
 253  /* Setup any mainboard PCI settings etc. */
 254  setup_mb_resource_map();
 255  post_code(0x36);
 256
 257  /* wait for all the APs core0 started by finalize_node_setup. */
 258  /* FIXME: A bunch of cores are going to start output to serial at once.
 259   * It would be nice to fixup prink spinlocks for ROM XIP mode.
 260   * I think it could be done by putting the spinlock flag in the cache
 261   * of the BSP located right after sysinfo.
 262   */
 263
 264         wait_all_core0_started();
 265 #if CONFIG_LOGICAL_CPUS==1
 266  /* Core0 on each node is configured. Now setup any additional cores. */
 267  printk(BIOS_DEBUG, "start_other_cores()\n");
 268         start_other_cores();
 269  post_code(0x37);
 270         wait_all_other_cores_started(bsp_apicid);
 271 #endif
 272
 273  post_code(0x38);
 274
 275 #if SET_FIDVID == 1
 276  msr = rdmsr(0xc0010071);
 277  printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 278
 279  /* FIXME: The sb fid change may survive the warm reset and only
 280   * need to be done once.*/
 281
 282         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 283  post_code(0x39);
 284
 285  if (!warm_reset_detect(0)) {      // BSP is node 0
 286    init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
 287  } else {
 288    init_fidvid_stage2(bsp_apicid, 0);  // BSP is node 0
 289         }
 290
 291  post_code(0x3A);
 292
 293  /* show final fid and vid */
 294  msr=rdmsr(0xc0010071);
 295  printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 296 #endif
 297
 298  wants_reset = mcp55_early_setup_x();
 299
 300  /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
 301  if (!warm_reset_detect(0)) {
 302    print_info("...WARM RESET...\n\n\n");
 303                 soft_reset();
 304    die("After soft_reset_x - shouldn't see this message!!!\n");
 305         }
 306
 307  if (wants_reset)
 308    printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n");
 309
 310  post_code(0x3B);
 311
 312 /* It's the time to set ctrl in sysinfo now; */
 313 printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
 314 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 315
 316 post_code(0x3D);
 317
 318 //printk(BIOS_DEBUG, "enable_smbus()\n");
 319 //        enable_smbus(); /* enable in sio_setup */
 320
 321 post_code(0x40);
 322
 323  printk(BIOS_DEBUG, "raminit_amdmct()\n");
 324  raminit_amdmct(sysinfo);
 325  post_code(0x41);
 326
 327 // printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
 328  post_cache_as_ram();  // BSP switch stack to ram, copy then execute LB.
 329  post_code(0x42);  // Should never see this post code.
 330
 331 }
 332